E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
2.4.6.1 Power Architecture VLE Mode Instruction Syndrome
The ESR[VLEMI] bit is provided to indicate that an interrupt was caused by a Power Architecture VLE
instruction. This syndrome bit is set on an exception associated with execution or attempted execution of
a Power Architecture VLE instruction. This bit is updated for the interrupt types indicated in Table 2-6.
2.4.6.2 Misaligned Instruction Fetch Syndrome
The ESR[MIF] bit is provided to indicate that an Instruction Storage Interrupt was caused by an attempt
to fetch an instruction from a Book E page which was not aligned on a word boundary. The fetch may have
been caused by execution of a Branch class instruction from a VLE page to a non-VLE page, a Branch to
LR instruction with LR[62]=1, a Branch to CTR instruction with CTR[62]=1, execution of an rfi or se_rfi
instruction with SRR0[62]=1, execution of an rfci or se_rfci instruction with CSRR0[62]=1, or execution
of an rfdi or se_rfdi instruction with DSRR0[62]=1, where the destination address corresponds to an
instruction page which is not marked as a Power Architecture VLE page.
The ESR[MIF] bit is also used to indicate that an Instruction TLB Interrupt was caused by a TLB miss on
the second half of a misaligned 32-bit Power Architecture VLE Instruction. For this case, SRR0 points to
the first half of the instruction, which resides on the previous page from the miss at page offset 0xFFE. The
ITLB handler may need to realize that the miss corresponds to the next page, although MMU MAS2
contents correctly reflects the page corresponding to the miss.
2.4.6.3 Precise External Termination Error Syndrome
The ESR[XTE] bit is provided to indicate that a precise external termination error DSI or ISI interrupt was
caused by an instruction. This syndrome bit is set on an external termination error exception that is
reported in a precise manner via a DSI or ISI as opposed to a machine check.
2.4.7 Machine Check Syndrome Register (MCSR)
When the core complex takes a machine check interrupt, it updates the Machine Check Syndrome register
(MCSR) to differentiate between machine check conditions. The MCSR is shown in Figure 2-10.
e200z1
MCP
0
CP_PERR
CPERR
EXCP_ERR
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-14 Freescale Semiconductor
0
BUS_IRERR
BUS_DRERR
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR—572; Read/Write; Reset —0x0
Figure 2-10. Machine Check Syndrome Register (MCSR)
BUS_WRERR
0