E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

e200z1 Overview
.
OnCE/NEXUS
CONTROL LOGIC
ADDRESS
MEMORY
MANAGEMENT
UNIT
32 32 N
DATA CONTROL
INSTRUCTION BUS INTERFACE UNIT
ADDRESS
1.1.2.1 Instruction Unit Features
The features of the e200 Instruction unit are:
CPU
CONTROL LOGIC
SPR
LR
CR
CTR
XER
INSTRUCTION UNIT
INSTRUCTION BUFFER
PC
UNIT
LOAD/
STORE
UNIT
DATA
BRANCH
UNIT
Figure 1-1. e200z1 Block Diagram
32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or up to two
16-bit VLE instructions per clock.
e200z1 Power Architecture Core Reference Manual, Rev. 0
1-4 Freescale Semiconductor
GPR
DATA BUS INTERFACE UNIT
32 32 N
CONTROL
INTEGER
EXECUTION
UNIT
MULTIPLY
UNIT
EXTERNAL
SPR
INTERFACE
(MTSPR/MFSPR)
CONTROL
DATA