E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
2.1 Power Architecture Book E Registers
e200 supports most of the registers defined by Power Architecture Book E Specification. Notable
exceptions are the Floating Point registers FPR0–FPR31 and FPSCR. e200does not support the Book E
floating-point architecture in hardware. The e200-supported Power Architecture Book E registers are
described as follows (e200-specific registers are described in the Section 2.2, “e200-Specific Special
Purpose Registers”).
User-level registers—The user-level registers can be accessed by all software with either user or
supervisor privileges. They include the following:
— General-purpose registers (GPRs). The thirty-two 32-bit GPRs (GPR0–GPR31) serve as data
source or destination registers for integer instructions and provide data for generating
addresses.
— Condition register (CR). The 32-bit CR consists of eight 4-bit fields, CR0–CR7, that reflect
results of certain arithmetic operations and provide a mechanism for testing and branching. See
“Condition Register (CR),” in Chapter 3, “Branch and Condition Register Operations, Power
Architecture Book E Specification.
The remaining user-level registers are SPRs. Note that the Power Architecture Book E provides the
mtspr and mfspr instructions for accessing SPRs.
— Integer exception register (XER). The XER indicates overflow and carries for integer
operations. See “XER Register (XER),” in Chapter 4, “Integer Operations” of Power
Architecture Book E Specification for more information.
— Link register (LR). The LR provides the branch target address for the Branch [Conditional] to
Link Register (bclr, bclrl, se_blr, se_blrl) instructions, and is used to hold the address of the
instruction that follows a branch and link instruction, typically used for linking to subroutines.
See “Link Register (LR)”, in Chapter 3, “Branch and Condition Register Operations” of Power
Architecture Book E Specification.
— Count register (CTR). The CTR holds a loop count that can be decremented during execution
of appropriately coded branch instructions. The CTR also provides the branch target address
for the Branch [Conditional] to Count Register (bcctr, bcctrl, se_bctr, se_bctrl) instructions.
See “Count Register (CTR)”, in Chapter 3, “Branch and Condition Register Operations” of
Power Architecture Book E Specification.
— The Time Base facility (TB) consists of two 32-bit registers—Time Base Upper (TBU) and
Time Base Lower (TBL). These two registers are accessible in a read-only fashion to user-level
software. See “Time Base”, in Chapter 8, “Timer Facilities” of Power Architecture Book E
Specification.
— SPRG4–SPRG7. The Power Architecture Book E architecture defines Software-Use Special
Purpose Registers (SPRGs). SPRG4 through SPRG7 are accessible in a read-only fashion by
user-level software. e200 does not allow user mode access to the SPRG3 register (defined as
implementation dependent by Book E).
— USPRG0. The PowerPC Book E architecture defines User Software-Use Special Purpose
Register USPRG0 which is accessible in a read-write fashion by user-level software.
Supervisor-level registers—In addition to the registers accessible in user mode, Supervisor-level
software has access to additional control and status registers used for configuration, exception
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-4 Freescale Semiconductor