E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Figures
Figure
Number Title
e200z1 Power Architecture Core Reference Manual, Rev. 0
Page
Number
A-13 Hardware Implementation Dependent Register 0 (HID0) ..................................................... A-4
A-14 Hardware Implementation Dependent Register 1 (HID1) ..................................................... A-4
A-15 Branch Unit Control and Status Register (BUCSR) .............................................................. A-4
A-16 Context Control Register (CTXCR) ...................................................................................... A-5
A-17 e200 Interrupt Vector Offset Register (IVOR)....................................................................... A-5
A-18 DBCNT Register.................................................................................................................... A-5
A-20 DBCR1 Register .................................................................................................................... A-5
A-21 DBCR2 Register .................................................................................................................... A-5
A-22 DBCR3 Register .................................................................................................................... A-5
A-23 DBSR Register....................................................................................................................... A-6
A-24 OnCE Status Register............................................................................................................. A-6
A-25 OnCE Command Register...................................................................................................... A-6
A-26 OnCE Control Register .......................................................................................................... A-6
A-27 CPU Scan Chain Register (CPUSCR) ................................................................................... A-7
A-28 Control State Register (CTL)................................................................................................. A-7
A-29 L1 Cache Configuration Register 0 (L1CFG0)...................................................................... A-7
A-30 MMU Configuration Register (MMUCFG) .......................................................................... A-8
A-31 TLB Configuration Registers (TLB0CFG, TLB1CFG)......................................................... A-8
A-32 MMU Control and Status Register 0 (MMUCSR0) .............................................................. A-8
A-34 Parallel Signature Control Register (PSCR) .......................................................................... A-9
A-33 MMU Assist Registers Summary .......................................................................................... A-9
A-35 Parallel Signature Status Register (PSSR) ........................................................................... A-10
A-36 Parallel Signature Low Register (PSLR) ............................................................................. A-10
A-37 Parallel Signature Counter Register (PSCTR) ..................................................................... A-10
A-38 Parallel Signature Update Low Register (PSULR).............................................................. A-10
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