E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
Mnemonic Name
Table 2-15. Special Purpose Registers (continued)
SPR
Number
DBCR0 Debug Control Register 0 308 R/W Yes No
DBCR1 Debug Control Register 1 309 R/W Yes No
DBCR2 Debug Control Register 2 310 R/W Yes No
DBCR3 Debug control register 3 561 R/W Yes Yes
DBSR Debug Status Register 304 Read/Clear 1
e200z1 Power Architecture Core Reference Manual, Rev. 0
Access Privileged
Zen
Specific
Yes No
DEAR Data Exception Address Register 61 R/W Yes No
DEC Decrementer 22 R/W Yes No
DECAR Decrementer Auto-Reload 54 R/W Yes No
DSRR0 Debug save/restore register 0 574 R/W Yes Yes
DSRR1 Debug save/restore register 1 575 R/W Yes Yes
ESR Exception Syndrome Register 62 R/W Yes No
HID0 Hardware implementation dependent reg 0 1008 R/W Yes Yes
HID1 Hardware implementation dependent reg 1 1009 R/W Yes Yes
IAC1 Instruction Address Compare 1 312 R/W Yes No
IAC2 Instruction Address Compare 2 313 R/W Yes No
IAC3 Instruction Address Compare 3 314 R/W Yes No
IAC4 Instruction Address Compare 4 315 R/W Yes No
IVPR Interrupt Vector Prefix Register 63 R/W Yes No
LR Link Register 8 R/W No No
L1CFG0 L1 cache config register 0 515 Read-only No Yes
MAS0 MMU assist register 0 624 R/W Yes Yes
MAS1 MMU assist register 1 625 R/W Yes Yes
MAS2 MMU assist register 2 626 R/W Yes Yes
MAS3 MMU assist register 3 627 R/W Yes Yes
MAS4 MMU assist register 4 628 R/W Yes Yes
MAS6 MMU assist register 6 630 R/W Yes Yes
MCSR Machine Check Syndrome Register 572 R/W Yes Yes
MMUCFG MMU configuration register 1015 Read-only Yes Yes
MMUCSR MMU control and status register 0 1012 R/W Yes Yes
PID0 Process ID Register 48 R/W Yes No
PIR Processor ID Register 286 Read-only Yes No
PVR Processor Version Register 287 Read-only Yes No
2-24 Freescale Semiconductor