E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

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Figures Figure Number Title e200z1 Power Architecture Core Reference Manual, Rev. 0 Page Number 5-4 e200 Interrupt Vector Prefix Register (IVPR)......................................................................... 5-9 5-5 e200 Interrupt Vector Addresses ............................................................................................. 5-9 6-1 Virtual Address and TLB-Entry Compare Process ................................................................. 6-2 6-2 Effective to Real Address Translation Flow ........................................................................... 6-3 6-3 Granting of Access Permission ............................................................................................... 6-5 6-4 MMU Configuration Register (MMUCFG) ........................................................................... 6-6 6-5 TLB0 Configuration Register (TLB0CFG) ............................................................................ 6-7 6-6 TLB1 Configuration Register (TLB1CFG) ............................................................................ 6-8 6-7 DEAR Register ..................................................................................................................... 6-14 6-8 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 6-15 6-9 MMU Assist Register 0 (MAS0) .......................................................................................... 6-16 6-10 MMU Assist Register 1 (MAS1) .......................................................................................... 6-16 6-11 MMU Assist Register 2 (MAS2) .......................................................................................... 6-18 6-12 MMU Assist Register 3 (MAS3) .......................................................................................... 6-19 6-13 MMU Assist Register 4 (MAS4) .......................................................................................... 6-19 6-14 MMU Assist Register 6 (MAS6) .......................................................................................... 6-20 6-15 MMU Assist Registers Summary ......................................................................................... 6-21 7-1 e200z1 Signal Groups ............................................................................................................. 7-3 7-2 Example External JTAG Register Design............................................................................. 7-34 7-3 Basic Read Transfers............................................................................................................. 7-37 7-4 Read Transfer with Wait-State .............................................................................................. 7-39 7-5 Basic Write Transfers............................................................................................................ 7-40 7-6 Write Transfer with Wait-State ............................................................................................. 7-42 7-7 Single Cycle Read and Write Transfers ................................................................................ 7-43 7-8 Single Cycle Read and Write Transfers—2 .......................................................................... 7-44 7-9 Multi-Cycle Read and Write Transfers ................................................................................. 7-45 7-10 Multi-Cycle Read and Write Transfers—2 ........................................................................... 7-46 7-11 Misaligned Read Transfer ..................................................................................................... 7-47 7-12 Misaligned Write Transfer .................................................................................................... 7-48 7-13 Misaligned Write, Single Cycle Read Transfer..................................................................... 7-49 7-14 Burst Read Transfer .............................................................................................................. 7-50 7-15 Burst Read with Wait-State Transfer..................................................................................... 7-51 7-16 Burst Write Transfer.............................................................................................................. 7-52 7-17 Burst Write with Wait-State Transfer.................................................................................... 7-53 7-18 Burst Read Transfers............................................................................................................. 7-54 7-19 Burst Read with Wait-State Transfer, Retraction .................................................................. 7-55 7-20 Burst Write Transfers, Single Beat Burst.............................................................................. 7-56 7-21 Read Transfer with Wait-State, Address Retraction ............................................................. 7-57 7-22 Burst Read with Wait-State Transfer, Retraction .................................................................. 7-58 7-23 Read and Write Transfers, Instr. Read Error Termination..................................................... 7-59 7-24 Data Read Error Termination................................................................................................ 7-60 xiv Freescale Semiconductor
Figures Figure Number Title e200z1 Power Architecture Core Reference Manual, Rev. 0 Page Number 7-25 Misaligned Write Error Termination..................................................................................... 7-61 7-26 Wakeup Control Signal (p_wakeup) ..................................................................................... 7-61 7-27 Interrupt Interface Input Signals ...........................................................................................7-62 7-28 e200 Interrupt Pending Operation......................................................................................... 7-62 7-29 Interrupt Acknowledge Operation ........................................................................................ 7-63 7-30 Interrupt Acknowledge Operation—2 .................................................................................. 7-64 7-31 Time Base Input Timing........................................................................................................ 7-65 7-32 Test Clock Input Timing ....................................................................................................... 7-65 7-33 j_trst_b Timing...................................................................................................................... 7-65 7-34 Test Access Port Timing ....................................................................................................... 7-66 9-1 e200 Debug Resources............................................................................................................ 9-3 9-2 DBCNT Register................................................................................................................... 9-10 9-3 DBCR0 Register ................................................................................................................... 9-10 9-4 DBCR1 Register ................................................................................................................... 9-13 9-5 DBCR2 Register ................................................................................................................... 9-15 9-6 DBCR3 Register ................................................................................................................... 9-18 9-7 DBSR Register...................................................................................................................... 9-22 9-8 OnCE TAP Controller and Registers .................................................................................... 9-25 9-9 e200 OnCE Controller and Serial Interface .......................................................................... 9-30 9-10 OnCE Status Register............................................................................................................ 9-30 9-11 OnCE Command Register..................................................................................................... 9-32 9-12 OnCE Control Register ......................................................................................................... 9-34 9-13 CPU Scan Chain Register (CPUSCR) .................................................................................. 9-40 9-14 Control State Register (CTL)................................................................................................9-41 9-15 Parallel Signature Control Register (PSCR) ......................................................................... 9-48 9-16 Parallel Signature Status Register (PSSR) ............................................................................ 9-49 9-17 Parallel Signature Low Register (PSLR) .............................................................................. 9-50 9-18 Parallel Signature Counter Register (PSCTR) ...................................................................... 9-50 9-19 Parallel Signature Update Low Register (PSULR)............................................................... 9-50 A-1 e200 User Mode Registers .....................................................................................................A-1 A-2 e200 Supervisor Mode Registers ........................................................................................... A-2 A-3 e200 Supervisor Mode Device Control Registers (DCR)...................................................... A-3 A-4 Machine State Register (MSR) .............................................................................................. A-3 A-5 Processor ID Register (PIR)................................................................................................... A-3 A-6 Processor Version Register (PVR) ......................................................................................... A-3 A-7 System Version Register (SVR)............................................................................................. A-3 A-8 Integer Exception Register (XER) ......................................................................................... A-3 A-9 Exception Syndrome Register (ESR)..................................................................................... A-4 A-10 Machine Check Syndrome Register (MCSR)........................................................................ A-4 A-11 Timer Control Register (TCR) ............................................................................................... A-4 A-12 Timer Status Register (TSR) .................................................................................................. A-4 Freescale Semiconductor xv
Page 1 and 2: e200z1 Power Architecture Core Refe
Page 3 and 4: Contents Paragraph Number Title Con
Page 5 and 6: Contents Paragraph Number Title e20
Page 13: Figures Figure Number Title e200z1
Page 17 and 18: Tables Table Number Title e200z1 Po
Page 19 and 20: Tables Table Number Title e200z1 Po
Page 21 and 22: Chapter 1 e200z1 Overview 1.1 Overv
Page 27 and 28: Chapter 2 Register Model This secti
Page 29 and 30: PSU Registers 1 PSU PSCR PSSR PSHR
Page 35 and 36: 17 (49) 18 (50) 19 (51) 20 (52) 21
Page 39 and 40: 8 (40) 9 (41) 10 (42) 11 (43) 12 (4
Page 43 and 44: 2.4.9 Timer Status Register (TSR) e
Page 45 and 46: 14 ICR Interrupt Inputs Clear Reser
Page 47 and 48: 2.4.13 Branch Unit Control and Stat
Page 49 and 50: Table 2-14. Additional Synchronizat
Page 51 and 52: Mnemonic Name Table 2-15. Special P
Page 53 and 54: Table 2-16. Reset Settings for e200
Page 55 and 56: Chapter 3 Instruction Model This ch
Page 57 and 58: 3.5 Memory Access Alignment Support
Page 63 and 64: 3.12.1 Instruction Index Sorted by
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Format Primary (Inst 0:5) Opcode e2
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Format Primary (Inst 0:5) Opcode X
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Format Primary (Inst 0:5) Opcode X
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Format Primary (Inst 0:5) Opcode XL
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Format Primary (Inst 0:5) Opcode Ta
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Format Primary (Inst0:5) Opcode Ext
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e200z1 Power Architecture Core Refe
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Chapter 4 Instruction Pipeline and
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4.1.2 Instruction Unit e200z1 Power
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Figure 4-2. Pipeline Diagram 4.3.1
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Time Slot 1st LD inst. IFETCH DEC /
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4.5.1 Completion Serialization e200
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4.7 Instruction Timings e200z1 Powe
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Chapter 5 Interrupts and Exceptions
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Interrupt Type e200z1 Power Archite
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14 (46) 15 (47) 16:23 (48:55) 5.3 M
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23 (55) 24 (56) 25 (57) 26 (58) 27
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MSR UCLE 0 WE 0 CE 0 EE 0 PR 0 ESR
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5.7.5 External Input Interrupt (IVO
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Table 5-18 lists register settings
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Table 5-21 lists register settings
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21 22 3 23 24 25 Data Storage 1. Ac
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Chapter 6 Memory Management Unit 6.
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21:25 [53:57] 26:27 [58:59] 28:29 [
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6.5 Software Interface and TLB Inst
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6.5.4 TLB Invalidate (tlbivax) Inst
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6.7.2 MMU Control and Status Regist
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Table 6-10. MAS1—Descriptor Conte
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The MAS3 register is shown in Figur
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6.7.4 MAS Registers Summary The MAS
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6.9 Core Interface Operation for MM
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Chapter 7 Core Complex Interfaces T
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Address Bus Transfer Control Transf
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Table 7-1. External Interface Signa
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j_lsrl_regsel O 0 External LSRL reg
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p_sprnum[0:9] O — Global SPR addr
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7.3.4.1 Transfer Type (p_d_htrans[1
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Table 7-8. p_[d,i]_hprot[5:0] Prote
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B. E. Word @001 0 0 1 1 0 0 B. E. W
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0 1 1 0 1 x x Reserved 0 1 1 1 0 x
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7.3.12.2 Processor Halt Request (p_
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7.3.14.1 OnCE Enable (jd_en_once) e
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1 j_tdo_en is asserted when the TAP
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7.3.15.14 Register Select (j_gp_reg
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Clock 2 (C2): e200z1 Power Architec
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7.4.1.5 Read and Write Transfers Fi
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7.4.1.6 Misaligned Accesses e200z1
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Figure 7-15 illustrates functional
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Figure 7-15 illustrates functional
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m_clk p_htrans p_addr,p_hprot p_hsi
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m_clk p_tbclk p_tbdisable t_tbclk_h
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Chapter 8 Power Management 8.1 Powe
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Chapter 9 Debug Support This chapte
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9.2.1 Instruction Address Compare E
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9.2.5 Branch Taken Debug Event e200
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9.2.13 Unconditional Debug Event e2
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Table 9-1 provides bit definitions
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9.3.3.2 Debug Control Register 1 (D
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9.3.3.3 Debug Control Register 2 (D
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Table 9-4. DBCR3 Bit Definitions (c
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posted, but the counter value will
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Table 9-9 indicates the e200 OnCE r
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Table 9-11 provides a list of acces
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9.4.7.4 Debug Request During Waitin
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9.4.8.2 Control State Register (CTL
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IRStat5—IR Status Bit 5 IRStat6
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To single-step the CPU: e200z1 Powe
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. 9.7.2 Parallel Signature Status R
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Appendix A Register Summary Conditi
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e200 z1 0 Figure A-3. e200 Supervis
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0 e200z1 Power Architecture Core Re
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* Figure A-27. CPU Scan Chain Regis
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M A S 0 M A S 1 M A S 2 M A S 3 M A
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Appendix B Revision History This ap
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Glossary The glossary contains an a
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Copy-back operation. A cache operat
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Local access window. Mapping used t
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Physical medium attachment (PMA) su
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Set (n). A subdivision of a cache.
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A Alignment exception, 5-15 B Branc
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