E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

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e200z1 Overview 32-bit Virtual and Physical Addresses 8-bit Process Identifier 8-entry Fully-associative TLB Support for multiple page sizes from 4-Kbyte to 4-Gbyte Entry Flush Protection e200z1 Power Architecture Core Reference Manual, Rev. 0 1-6 Freescale Semiconductor
Chapter 2 Register Model This section describes the registers implemented in the e200z1 core. It includes an overview of registers defined by the PowerPC Book E architecture, highlighting differences in how these registers are implemented in the e200 core, and provides a detailed description of e200-specific registers. Full descriptions of the architecture-defined register set are provided in Power Architecture Book E Specification. The Power Architecture Book E defines register-to-register operations for all computational instructions. Source data for these instructions are accessed from the on-chip registers or are provided as immediate values embedded in the opcode. The three-register instruction format allows specification of a target register distinct from the two source registers, thus preserving the original data for use by other instructions. Data is transferred between memory and registers with explicit load and store instructions only. Figure 2-1, Figure 2-2, and Figure 2-3 show the e200 register set including the registers which are accessible while in supervisor mode, and the registers which are accessible in user mode. The number to the right of the special-purpose registers (SPRs) is the decimal number used in the instruction syntax to access the register (for example, the integer exception register (XER) is SPR 1). NOTE e200z1 is a 32-bit implementation of the Power Architecture Book E specification. In this document, register bits are sometimes numbered from bit 0 (Most Significant Bit) to 31 (Least Significant Bit), rather than the Book E numbering scheme of 32:63, thus register bit numbers for some registers in Book E are 32 higher. Where appropriate, the Book E defined bit numbers are shown in parentheses. e200z1 Power Architecture Core Reference Manual, Rev. 0 Freescale Semiconductor 2-1
Page 1 and 2: e200z1 Power Architecture Core Refe
Page 3 and 4: Contents Paragraph Number Title Con
Page 5 and 6: Contents Paragraph Number Title e20
Page 13 and 14: Figures Figure Number Title e200z1
Page 15 and 16: Figures Figure Number Title e200z1
Page 17 and 18: Tables Table Number Title e200z1 Po
Page 19 and 20: Tables Table Number Title e200z1 Po
Page 21 and 22: Chapter 1 e200z1 Overview 1.1 Overv
Page 25: e200z1 Power Architecture Core Refe
Page 29 and 30: PSU Registers 1 PSU PSCR PSSR PSHR
Page 35 and 36: 17 (49) 18 (50) 19 (51) 20 (52) 21
Page 39 and 40: 8 (40) 9 (41) 10 (42) 11 (43) 12 (4
Page 43 and 44: 2.4.9 Timer Status Register (TSR) e
Page 45 and 46: 14 ICR Interrupt Inputs Clear Reser
Page 47 and 48: 2.4.13 Branch Unit Control and Stat
Page 49 and 50: Table 2-14. Additional Synchronizat
Page 51 and 52: Mnemonic Name Table 2-15. Special P
Page 53 and 54: Table 2-16. Reset Settings for e200
Page 55 and 56: Chapter 3 Instruction Model This ch
Page 57 and 58: 3.5 Memory Access Alignment Support
Page 63 and 64: 3.12.1 Instruction Index Sorted by
Page 65 and 66: Format Primary (Inst 0:5) Opcode e2
Page 67 and 68: Format Primary (Inst 0:5) Opcode X
Page 69 and 70: Format Primary (Inst 0:5) Opcode X
Page 71 and 72: Format Primary (Inst 0:5) Opcode XL
Page 73 and 74: Format Primary (Inst 0:5) Opcode Ta
Page 75 and 76: Format Primary (Inst0:5) Opcode Ext
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Format Primary (Inst0:5) Opcode Ext
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e200z1 Power Architecture Core Refe
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Chapter 4 Instruction Pipeline and
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4.1.2 Instruction Unit e200z1 Power
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Figure 4-2. Pipeline Diagram 4.3.1
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Time Slot 1st LD inst. IFETCH DEC /
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4.5.1 Completion Serialization e200
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4.7 Instruction Timings e200z1 Powe
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Chapter 5 Interrupts and Exceptions
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Interrupt Type e200z1 Power Archite
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14 (46) 15 (47) 16:23 (48:55) 5.3 M
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23 (55) 24 (56) 25 (57) 26 (58) 27
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MSR UCLE 0 WE 0 CE 0 EE 0 PR 0 ESR
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5.7.5 External Input Interrupt (IVO
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Table 5-18 lists register settings
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Table 5-21 lists register settings
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21 22 3 23 24 25 Data Storage 1. Ac
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Chapter 6 Memory Management Unit 6.
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21:25 [53:57] 26:27 [58:59] 28:29 [
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6.5 Software Interface and TLB Inst
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6.5.4 TLB Invalidate (tlbivax) Inst
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6.7.2 MMU Control and Status Regist
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Table 6-10. MAS1—Descriptor Conte
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The MAS3 register is shown in Figur
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6.7.4 MAS Registers Summary The MAS
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6.9 Core Interface Operation for MM
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Chapter 7 Core Complex Interfaces T
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Address Bus Transfer Control Transf
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Table 7-1. External Interface Signa
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j_lsrl_regsel O 0 External LSRL reg
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p_sprnum[0:9] O — Global SPR addr
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7.3.4.1 Transfer Type (p_d_htrans[1
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Table 7-8. p_[d,i]_hprot[5:0] Prote
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B. E. Word @001 0 0 1 1 0 0 B. E. W
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0 1 1 0 1 x x Reserved 0 1 1 1 0 x
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7.3.12.2 Processor Halt Request (p_
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7.3.14.1 OnCE Enable (jd_en_once) e
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1 j_tdo_en is asserted when the TAP
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7.3.15.14 Register Select (j_gp_reg
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Clock 2 (C2): e200z1 Power Architec
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7.4.1.5 Read and Write Transfers Fi
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7.4.1.6 Misaligned Accesses e200z1
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Figure 7-15 illustrates functional
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Figure 7-15 illustrates functional
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m_clk p_htrans p_addr,p_hprot p_hsi
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m_clk p_tbclk p_tbdisable t_tbclk_h
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Chapter 8 Power Management 8.1 Powe
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Chapter 9 Debug Support This chapte
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9.2.1 Instruction Address Compare E
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9.2.5 Branch Taken Debug Event e200
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9.2.13 Unconditional Debug Event e2
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Table 9-1 provides bit definitions
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9.3.3.2 Debug Control Register 1 (D
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9.3.3.3 Debug Control Register 2 (D
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Table 9-4. DBCR3 Bit Definitions (c
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posted, but the counter value will
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Table 9-9 indicates the e200 OnCE r
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Table 9-11 provides a list of acces
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9.4.7.4 Debug Request During Waitin
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9.4.8.2 Control State Register (CTL
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IRStat5—IR Status Bit 5 IRStat6
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To single-step the CPU: e200z1 Powe
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. 9.7.2 Parallel Signature Status R
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Appendix A Register Summary Conditi
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e200 z1 0 Figure A-3. e200 Supervis
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0 e200z1 Power Architecture Core Re
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* Figure A-27. CPU Scan Chain Regis
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M A S 0 M A S 1 M A S 2 M A S 3 M A
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Appendix B Revision History This ap
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Glossary The glossary contains an a
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Copy-back operation. A cache operat
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Local access window. Mapping used t
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Physical medium attachment (PMA) su
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Set (n). A subdivision of a cache.
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A Alignment exception, 5-15 B Branc
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