E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
2.4.2 Processor ID Register (PIR)
The processor ID for the processor core is contained in the Processor ID Register (PIR), shown in
Figure 2-5. The contents of the PIR register are a reflection of hardware input signals to the e200 core. This
register is read-only.
The PIR fields are defined in Table 2-2.
2.4.3 Processor Version Register (PVR)
The Processor Version Register (PVR), shown in Figure 2-6, contains the processor version number for
the processor core.
The PVR bit fields are shown in Table 2-3.
0 ID
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR—286; Read-only
Figure 2-5. Processor ID Register (PIR)
Table 2-2. PIR Field Descriptions
Bits Name Description
0:23 — These bits always reads 0.
24:31 ID These bits are a reflection of the values provided on the p_cpuid[0:7] input signals.
1 0 0 0 0 0 Type Version MBG Reserved Major Rev MBG ID
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR—287; Read-only
Figure 2-6. Processor Version Register (PVR)
Table 2-3. PVR Field Descriptions
Bits Name Description
0–5 Reserved Reserved
6–11 Type A 6-bit number that, together with the version number, uniquely identifies a particular processor version.
12–15 Version A 4-bit number that, together with the version number, uniquely identifies a particular processor version.
16–23 Reserved Reserved
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-10 Freescale Semiconductor