E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
23 DAPUEN Debug APU enable
0 Debug APU disabled
1 Debug APU enabled
This bit controls whether the Debug APU is enabled. When enabled, Debug interrupts use the
DSRR0/DSRR1 registers for saving state, and the rfdi and se_rfdi instruction is available for
returning from a debug interrupt.
When disabled, Debug Interrupts use the critical interrupt resources CSRR0/CSRR1 for saving
state, the rfci and se_rfci instruction is used for returning from a debug interrupt, and the rfdi and
se_rfdi instruction is treated as an illegal instruction.
When disabled, the settings of the DCLREE, DCLRCE, CICLRDE, and MCCLRDE bits are ignored
and are assumed to be ‘1’s
Read and write access to DSRR0/DSRR1 via the mfspr and mtspr instructions is not affected by
this bit.
24:31 — Reserved 1
1 These bits are not implemented and should be written with zero for future compatibility.
2.4.12 Hardware Implementation Dependent Register 1 (HID1)
The HID1 register is used for bus configuration and system control. HID1 is shown in Figure 2-14.
The HID1 fields are defined in Table 2-11.
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-20 Freescale Semiconductor
SYSCTL
SPR—1009; Read/Write; Reset—0x0
Figure 2-14. Hardware Implementation Dependent Register 1 (HID1)
Table 2-11. Hardware Implementation Dependent Register 1
Bits Name Description
0:15 — Reserved 1
16:23 SYSCTL System Control
These bits are reflected on the outputs of the p_hid1_sysctl[0:7] output signals for use in controlling the
system. They may need external synchronization.
24 ATS Atomic status (read-only)
Indicates state of the reservation bit in the load/store unit. See Section 3.6, “Memory Synchronization and
Reservation Instructions,” for more detail.
25:31 — Reserved 1
Table 2-10. Hardware Implementation Dependent Register 0 (continued)
Bits Name Description
1 These bits are not implemented and should be written with zero for future compatibility.
ATS
0