E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
2.4.17 TLB Configuration Registers (TLB0CFG, TLB1CFG)
The TLB0CFG and TLB1CFG registers provide configuration information for the optional MMU TLBs
supplied with this version of the e200 CPU core. A description of these registers can be found in Chapter 6,
“Memory Management Unit.”
2.5 SPR Register Access
SPRs are accessed with the mfspr and mtspr instructions. The following sections outline additional access
requirements.
2.5.1 Invalid SPR References
System behavior when an invalid SPR is referenced depends on the apparent privilege level of the register.
The register privilege level is determined by bit 5 in the SPR address. If the invalid SPR is accessible in
user mode, then an illegal exception is generated. If the invalid SPR is accessible only in supervisor mode
and the CPU core is in supervisor mode (MSR[PR] = 0), then an illegal exception is generated. If the
invalid SPR address is accessible only in supervisor mode and the core is not in supervisor mode
(MSR[PR] = 1), then a privilege exception is generated.
Table 2-13. System Response to Invalid SPR Reference
SPR Address Bit 5 Mode MSR[PR] Response
0 — — Illegal exception
1 supervisor 0 Illegal exception
1 user 1 Privilege exception
References to the SPRs associated with an optional unit (Cache, MMU, EFPU) when the unit is not present
are treated as references to an invalid SPR unless otherwise defined.
2.5.2 Synchronization Requirements for SPRs
With the exception of the following registers, there are no synchronization requirements for accessing
SPRs beyond those stated in Power Architecture Book E. Software requirements for synchronization
before/after accessing these registers are shown in Table 2-14. The notation CSI in the table refers to a
Context Synchronizing instruction which include sc, isync, rfi, rfci, and rfdi.
Table 2-14. Additional Synchronization Requirements for SPRs
Context Altering Event or Instruction
mfspr
Required
Before
e200z1 Power Architecture Core Reference Manual, Rev. 0
Required
After
DBCNT Debug Counter register msync none 1
DBSR Debug Status Register msync none —
HID0 Hardware implementation dependent reg 0 none none —
2-22 Freescale Semiconductor
Notes