E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Tables
Table
Number Title
e200z1 Power Architecture Core Reference Manual, Rev. 0
Page
Number
5-15 Program Interrupt—Register Settings................................................................................... 5-17
5-16 Floating-Point Unavailable Interrupt—Register Settings..................................................... 5-17
5-17 System Call Interrupt—Register Settings ............................................................................. 5-18
5-18 Decrementer Interrupt—Register Settings............................................................................ 5-19
5-19 Fixed-Interval Timer Interrupt—Register Settings............................................................... 5-19
5-20 Watchdog Timer Interrupt—Register Settings...................................................................... 5-20
5-21 Data TLB Error Interrupt—Register Settings....................................................................... 5-21
5-22 Instruction TLB Error Interrupt—Register Settings ............................................................. 5-21
5-23 Debug Interrupt—Register Settings...................................................................................... 5-24
5-24 TSR Watchdog Timer Reset Status ....................................................................................... 5-25
5-25 DBSR Most Recent Reset ..................................................................................................... 5-25
5-26 System Reset Interrupt—Register Settings........................................................................... 5-25
5-27 e200 Exception Priorities ...................................................................................................... 5-27
5-28 MSR Setting Due to Interrupt ............................................................................................... 5-30
6-1 Page Size and EPN Field Comparison.................................................................................... 6-3
6-2 TLB Entry Bit Definitions ...................................................................................................... 6-5
6-3 MMUCFG Field Descriptions ................................................................................................ 6-6
6-4 TLB0CFG Field Descriptions................................................................................................. 6-7
6-5 TLB1CFG Field Descriptions................................................................................................. 6-8
6-6 tlbivax EA Bit Definitions .................................................................................................... 6-11
6-7 TLB Entry 0 Values after Reset ............................................................................................ 6-13
6-8 MMUCSR0—MMU Control and Status Register 0 ............................................................. 6-15
6-9 MAS0—MMU Read/Write and Replacement Control......................................................... 6-16
6-10 MAS1—Descriptor Context and Configuration Control...................................................... 6-17
6-11 MAS2—EPN and Page Attributes........................................................................................ 6-18
6-12 MAS3—RPN and Access Control........................................................................................ 6-19
6-13 MAS4—Hardware Replacement Assist Configuration Register.......................................... 6-19
6-14 MAS6—TLB Search Context Register 0.............................................................................. 6-20
6-15 MMU Assist Register Field Updates .................................................................................... 6-22
6-16 Transfer Type Encoding ........................................................................................................ 6-23
7-1 External Interface Signal Definitions...................................................................................... 7-4
7-2 Internal Interface Signal Definitions....................................................................................... 7-7
7-3 p_hrdata[31:0] Byte Address Mappings............................................................................... 7-12
7-4 p_d_hwdata[31:0] Byte Address Mappings ......................................................................... 7-12
7-5 p_[d,i]_htrans[1:0] Transfer Type Encoding........................................................................ 7-13
7-6 p_[d,i]_hsize[1:0] Transfer Size Encoding ........................................................................... 7-13
7-7 p_[d,i]_hburst[2:0] Burst Type Encoding............................................................................. 7-14
7-8 p_[d,i]_hprot[5:0] Protection Control Encoding .................................................................. 7-14
7-9 Mapping of Access Attributes to p_hprot[4:2] Protection Control....................................... 7-15
7-10 p_hbstrb[3:0] to Byte Address Mappings............................................................................. 7-16
7-11 Byte Strobe Assertion for Transfers...................................................................................... 7-17
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