E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

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Contents Paragraph Number Title e200z1 Power Architecture Core Reference Manual, Rev. 0 Page Number 7.3.4.2 Write (p_d_hwrite, p_i_hwrite) ............................................................................. 7-13 7.3.4.3 Transfer Size (p_d_hsize[1:0], p_i_hsize[1:0])...................................................... 7-13 7.3.4.4 Burst Type (p_d_hburst[2:0], p_i_hburst[2:0])..................................................... 7-14 7.3.4.5 Protection Control (p_d_hprot[5:0], p_i_hprot[5:0]) ............................................ 7-14 7.3.5 Byte Lane Specification............................................................................................. 7-15 7.3.5.1 Unaligned Access (p_d_hunalign, p_i_hunalign) ................................................. 7-16 7.3.5.2 Byte Strobes (p_d_hbstrb[3:0], p_i_hbstrb[3:0]) .................................................. 7-16 7.3.6 Transfer Control Signals............................................................................................ 7-19 7.3.6.1 Transfer Ready (p_d_hready, p_i_hready) ............................................................ 7-20 7.3.6.2 Transfer Response (p_d_hresp[2:0], p_i_hresp[1:0])............................................ 7-20 7.3.7 Interrupt Signals......................................................................................................... 7-20 7.3.7.1 External Input Interrupt Request (p_extint_b)....................................................... 7-21 7.3.7.2 Critical Input Interrupt Request (p_critint_b)........................................................ 7-21 7.3.7.3 Interrupt Pending (p_ipend)................................................................................... 7-21 7.3.7.4 Autovector (p_avec_b) .......................................................................................... 7-21 7.3.7.5 Interrupt Vector Offset (p_voffset[0:9]) ................................................................. 7-21 7.3.7.6 Interrupt Vector Acknowledge (p_iack) ................................................................ 7-22 7.3.7.7 Machine Check (p_mcp_b).................................................................................... 7-22 7.3.8 Timer Facility Signals................................................................................................ 7-22 7.3.8.1 Timer Disable (p_tbdisable) .................................................................................. 7-22 7.3.8.2 Timer External Clock (p_tbclk) ............................................................................. 7-22 7.3.8.3 Timer Interrupt Status (p_tbint) ............................................................................. 7-23 7.3.9 Processor Reservation Signals................................................................................... 7-23 7.3.9.1 CPU Reservation Status (p_rsrv)........................................................................... 7-23 7.3.9.2 CPU Reservation Clear (p_rsrv_clr) ..................................................................... 7-23 7.3.10 Miscellaneous Processor Signals ............................................................................... 7-23 7.3.10.1 PID0 Outputs (p_pid0[0:7])................................................................................... 7-24 7.3.10.2 PID0 Update (p_pid0_updt) .................................................................................. 7-24 7.3.10.3 HID1 System Control (p_hid1_sysctl[0:7])........................................................... 7-24 7.3.11 Processor State Signals .............................................................................................. 7-24 7.3.11.1 Processor Status (p_pstat[0:6]).............................................................................. 7-24 7.3.11.2 Processor Exception Enable MSR Values (p_EE, p_CE, p_DE, p_ME)............... 7-26 7.3.11.3 Branch Prediction Status (p_brstat[0:1])............................................................... 7-26 7.3.11.4 Processor Machine Check (p_mcp_out) ................................................................ 7-26 7.3.11.5 Processor Checkstop (p_chkstop).......................................................................... 7-26 7.3.12 Power Management Control Signals ......................................................................... 7-26 7.3.12.1 Processor Waiting (p_waiting)............................................................................... 7-26 7.3.12.2 Processor Halt Request (p_halt) ............................................................................ 7-27 7.3.12.3 Processor Halted (p_halted) .................................................................................. 7-27 7.3.12.4 Processor Stop Request (p_stop) ........................................................................... 7-27 7.3.12.5 Processor Stopped (p_stopped).............................................................................. 7-27 viii Freescale Semiconductor
Contents Paragraph Number Title e200z1 Power Architecture Core Reference Manual, Rev. 0 Page Number 7.3.12.6 Low-Power Mode Signals (p_doze, p_nap, p_sleep) ............................................ 7-27 7.3.12.7 Wakeup (p_wakeup) .............................................................................................. 7-27 7.3.13 Debug Event Signals.................................................................................................. 7-28 7.3.13.1 Unconditional Debug Event (p_ude) ..................................................................... 7-28 7.3.13.2 External Debug Event 1 (p_devt1) ........................................................................ 7-28 7.3.13.3 External Debug Event 2 (p_devt2) ........................................................................ 7-28 7.3.14 Debug/Emulation (Nexus 1/OnCE) Support Signals................................................. 7-28 7.3.14.1 OnCE Enable (jd_en_once) ................................................................................... 7-29 7.3.14.2 Debug Session (jd_debug_b)................................................................................. 7-29 7.3.14.3 Debug Request (jd_de_b) ...................................................................................... 7-30 7.3.14.4 DE_b Active High Output Enable (jd_de_en)....................................................... 7-30 7.3.14.5 Processor Clock On (jd_mclk_on) ......................................................................... 7-30 7.3.14.6 Watchpoint Events (jd_watchpoint[0:7])............................................................... 7-30 7.3.15 JTAG Support Signals ............................................................................................... 7-30 7.3.15.1 JTAG/OnCE Serial Input (j_tdi)............................................................................ 7-31 7.3.15.2 JTAG/OnCE Serial Clock (j_tclk) ......................................................................... 7-31 7.3.15.3 JTAG/OnCE Serial Output (j_tdo) ........................................................................ 7-31 7.3.15.4 JTAG/OnCE Test Mode Select (j_tms).................................................................. 7-31 7.3.15.5 JTAG/OnCE Test Reset (j_trst_b) ......................................................................... 7-31 7.3.15.6 Test-Logic-Reset (j_tst_log_rst)............................................................................ 7-32 7.3.15.7 Run-Test/Idle (j_rti)............................................................................................... 7-32 7.3.15.8 Capture IR (j_capture_ir) ...................................................................................... 7-32 7.3.15.9 Shift IR (j_shift_ir) ................................................................................................ 7-32 7.3.15.10 Update IR (j_update_ir) ........................................................................................ 7-32 7.3.15.11 Capture DR (j_capture_dr).................................................................................... 7-32 7.3.15.12 Shift DR (j_shift_dr).............................................................................................. 7-32 7.3.15.13 Update DR (j_update_gp_reg) .............................................................................. 7-32 7.3.15.14 Register Select (j_gp_regsel)................................................................................. 7-33 7.3.15.15 Enable Once Register Select (j_en_once_regsel).................................................. 7-33 7.3.15.16 External Nexus Register Select (j_nexus_regsel).................................................. 7-33 7.3.15.17 External LSRL Register Select (j_lsrl_regsel) ...................................................... 7-33 7.3.15.18 Serial Data (j_serial_data) .................................................................................... 7-34 7.3.15.19 Key Data In (j_key_in)........................................................................................... 7-34 7.3.16 JTAG ID Signals........................................................................................................ 7-35 7.3.16.1 JTAG ID Sequence (j_id_sequence[0:1]) .............................................................. 7-35 7.3.16.2 JTAG ID Sequence (j_id_sequence[2:9]) .............................................................. 7-36 7.3.16.3 JTAG ID Version (j_id_version[0:3]).................................................................... 7-36 7.4 Timing Diagrams ........................................................................................................... 7-36 7.4.1 Processor Instruction/Data Transfers......................................................................... 7-36 7.4.1.1 Basic Read Transfer Cycles................................................................................... 7-37 Clock 1 (C1): 38 Freescale Semiconductor ix
Page 1 and 2: e200z1 Power Architecture Core Refe
Page 3 and 4: Contents Paragraph Number Title Con
Page 5 and 6: Contents Paragraph Number Title e20
Page 7: Contents Paragraph Number Title e20
Page 11 and 12: Contents Paragraph Number Title e20
Page 13 and 14: Figures Figure Number Title e200z1
Page 15 and 16: Figures Figure Number Title e200z1
Page 17 and 18: Tables Table Number Title e200z1 Po
Page 19 and 20: Tables Table Number Title e200z1 Po
Page 21 and 22: Chapter 1 e200z1 Overview 1.1 Overv
Page 27 and 28: Chapter 2 Register Model This secti
Page 29 and 30: PSU Registers 1 PSU PSCR PSSR PSHR
Page 35 and 36: 17 (49) 18 (50) 19 (51) 20 (52) 21
Page 39 and 40: 8 (40) 9 (41) 10 (42) 11 (43) 12 (4
Page 43 and 44: 2.4.9 Timer Status Register (TSR) e
Page 45 and 46: 14 ICR Interrupt Inputs Clear Reser
Page 47 and 48: 2.4.13 Branch Unit Control and Stat
Page 49 and 50: Table 2-14. Additional Synchronizat
Page 51 and 52: Mnemonic Name Table 2-15. Special P
Page 53 and 54: Table 2-16. Reset Settings for e200
Page 55 and 56: Chapter 3 Instruction Model This ch
Page 57 and 58: 3.5 Memory Access Alignment Support
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e200z1 Power Architecture Core Refe
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3.12.1 Instruction Index Sorted by
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Format Primary (Inst 0:5) Opcode e2
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Format Primary (Inst 0:5) Opcode X
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Format Primary (Inst 0:5) Opcode X
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Format Primary (Inst 0:5) Opcode XL
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Format Primary (Inst 0:5) Opcode Ta
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Format Primary (Inst0:5) Opcode Ext
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Chapter 4 Instruction Pipeline and
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4.1.2 Instruction Unit e200z1 Power
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Figure 4-2. Pipeline Diagram 4.3.1
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Time Slot 1st LD inst. IFETCH DEC /
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4.5.1 Completion Serialization e200
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4.7 Instruction Timings e200z1 Powe
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Chapter 5 Interrupts and Exceptions
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Interrupt Type e200z1 Power Archite
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14 (46) 15 (47) 16:23 (48:55) 5.3 M
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23 (55) 24 (56) 25 (57) 26 (58) 27
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MSR UCLE 0 WE 0 CE 0 EE 0 PR 0 ESR
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5.7.5 External Input Interrupt (IVO
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Table 5-18 lists register settings
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Table 5-21 lists register settings
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21 22 3 23 24 25 Data Storage 1. Ac
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Chapter 6 Memory Management Unit 6.
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21:25 [53:57] 26:27 [58:59] 28:29 [
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6.5 Software Interface and TLB Inst
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6.5.4 TLB Invalidate (tlbivax) Inst
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6.7.2 MMU Control and Status Regist
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Table 6-10. MAS1—Descriptor Conte
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The MAS3 register is shown in Figur
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6.7.4 MAS Registers Summary The MAS
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6.9 Core Interface Operation for MM
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Chapter 7 Core Complex Interfaces T
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Address Bus Transfer Control Transf
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Table 7-1. External Interface Signa
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j_lsrl_regsel O 0 External LSRL reg
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p_sprnum[0:9] O — Global SPR addr
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7.3.4.1 Transfer Type (p_d_htrans[1
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Table 7-8. p_[d,i]_hprot[5:0] Prote
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B. E. Word @001 0 0 1 1 0 0 B. E. W
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0 1 1 0 1 x x Reserved 0 1 1 1 0 x
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7.3.12.2 Processor Halt Request (p_
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7.3.14.1 OnCE Enable (jd_en_once) e
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1 j_tdo_en is asserted when the TAP
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7.3.15.14 Register Select (j_gp_reg
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Clock 2 (C2): e200z1 Power Architec
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7.4.1.5 Read and Write Transfers Fi
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7.4.1.6 Misaligned Accesses e200z1
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Figure 7-15 illustrates functional
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Figure 7-15 illustrates functional
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m_clk p_htrans p_addr,p_hprot p_hsi
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m_clk p_tbclk p_tbdisable t_tbclk_h
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Chapter 8 Power Management 8.1 Powe
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Chapter 9 Debug Support This chapte
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9.2.1 Instruction Address Compare E
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9.2.5 Branch Taken Debug Event e200
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9.2.13 Unconditional Debug Event e2
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Table 9-1 provides bit definitions
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9.3.3.2 Debug Control Register 1 (D
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9.3.3.3 Debug Control Register 2 (D
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Table 9-4. DBCR3 Bit Definitions (c
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posted, but the counter value will
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Table 9-9 indicates the e200 OnCE r
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Table 9-11 provides a list of acces
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9.4.7.4 Debug Request During Waitin
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9.4.8.2 Control State Register (CTL
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IRStat5—IR Status Bit 5 IRStat6
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To single-step the CPU: e200z1 Powe
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. 9.7.2 Parallel Signature Status R
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Appendix A Register Summary Conditi
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e200 z1 0 Figure A-3. e200 Supervis
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0 e200z1 Power Architecture Core Re
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* Figure A-27. CPU Scan Chain Regis
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M A S 0 M A S 1 M A S 2 M A S 3 M A
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Appendix B Revision History This ap
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Glossary The glossary contains an a
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Copy-back operation. A cache operat
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Local access window. Mapping used t
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Physical medium attachment (PMA) su
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Set (n). A subdivision of a cache.
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A Alignment exception, 5-15 B Branc
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