E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

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Contents Paragraph Number Title e200z1 Power Architecture Core Reference Manual, Rev. 0 Page Number 9.4.7 Methods of Entering Debug Mode ............................................................................ 9-38 9.4.7.1 External Debug Request During RESET............................................................... 9-38 9.4.7.2 Debug Request During RESET ............................................................................. 9-38 9.4.7.3 Debug Request During Normal Activity ............................................................... 9-38 9.4.7.4 Debug Request During Waiting, Halted or Stopped State..................................... 9-39 9.4.7.5 Software Request During Normal Activity ........................................................... 9-39 9.4.8 CPU Status and Control Scan Chain Register (CPUSCR) ........................................ 9-39 9.4.8.1 Instruction Register (IR) ........................................................................................ 9-40 9.4.8.2 Control State Register (CTL)................................................................................. 9-41 9.4.8.3 Program Counter Register (PC)............................................................................. 9-44 9.4.8.4 Write-Back Bus Register (WBBRlow, WBBRhigh) ............................................. 9-44 9.4.8.5 Machine State Register (MSR).............................................................................. 9-45 9.4.9 Reserved Registers (Reserved) .................................................................................. 9-45 9.5 Watchpoint Support ....................................................................................................... 9-45 9.6 Basic Steps for Enabling, Using, and Exiting External Debug Mode ........................... 9-46 9.7 Parallel Signature Unit................................................................................................... 9-47 9.7.1 Parallel Signature Control Register (PSCR).............................................................. 9-48 9.7.2 Parallel Signature Status Register (PSSR)................................................................. 9-49 9.7.3 Parallel Signature Low Register (PSLR) ................................................................... 9-50 9.7.4 Parallel Signature Counter Register (PSCTR)........................................................... 9-50 9.7.5 Parallel Signature Update Low Register (PSULR).................................................... 9-50 Appendix A Register Summary Appendix B Revision History Glossary xii Freescale Semiconductor
Figures Figure Number Title e200z1 Power Architecture Core Reference Manual, Rev. 0 Page Number Figures 1-1 e200z1 Block Diagram............................................................................................................ 1-4 2-1 e200z1 Supervisor Mode Programmer’s Model SPRs............................................................ 2-2 2-2 e200 Supervisor Mode Program Model Device Control Registers (DCRs) ........................... 2-3 2-3 e200 User Mode Program Model............................................................................................ 2-3 2-4 Machine State Register (MSR) ............................................................................................... 2-8 2-5 Processor ID Register (PIR)..................................................................................................2-10 2-6 Processor Version Register (PVR) ........................................................................................ 2-10 2-7 System Version Register (SVR)............................................................................................ 2-11 2-8 Integer Exception Register (XER) ........................................................................................ 2-11 2-9 Exception Syndrome Register (ESR).................................................................................... 2-12 2-10 Machine Check Syndrome Register (MCSR)....................................................................... 2-14 2-11 Timer Control Register (TCR) .............................................................................................. 2-15 2-12 Timer Status Register (TSR) .................................................................................................2-17 2-13 Hardware Implementation Dependent Register 0 (HID0) .................................................... 2-18 2-14 Hardware Implementation Dependent Register 1 (HID1) .................................................... 2-20 2-15 Branch Unit Control and Status Register (BUCSR) ............................................................. 2-21 4-1 e200z1 Block Diagram............................................................................................................ 4-2 4-2 Pipeline Diagram..................................................................................................................... 4-5 4-3 e200 Instruction Buffers.......................................................................................................... 4-6 4-4 e200 Branch Target Buffer...................................................................................................... 4-8 4-5 Basic Pipeline Flow, Single Cycle Instructions ...................................................................... 4-8 4-6 A Load Followed By A Dependent Add Instruction .............................................................. 4-9 4-7 Back-to-back Load Instructions .............................................................................................. 4-9 4-8 A Load Followed By A Dependent Store Instruction........................................................... 4-10 4-9 Basic Pipeline Flow, Branch Instructions ............................................................................. 4-10 4-10 Basic Pipeline Flow, Branch Speculation ............................................................................. 4-11 4-11 Basic Pipeline Flow, Multi-cycle Instructions ...................................................................... 4-11 4-12 Pipelined Load/Store Instructions ......................................................................................... 4-12 4-13 Pipelined Load/Store Instructions with Wait-state................................................................ 4-12 4-14 mtspr, mfspr Instruction Execution—(1) .............................................................................. 4-13 4-15 mtmsr, wrtee, wrteei Instruction Execution .......................................................................... 4-13 4-16 DCR, MMU mtspr, mfspr and MMU Management Instruction Execution.......................... 4-14 4-17 Interrupt Recognition and Handler Instruction Execution.................................................... 4-16 4-18 Interrupt Recognition and Handler Instruction Execution—Load/Store in Progress ........... 4-17 4-19 Interrupt Recognition and Handler Instruction Execution—Multi-Cycle Instruction Abort 4-18 5-1 Exception Syndrome Register (ESR)...................................................................................... 5-4 5-2 Machine State Register (MSR) ............................................................................................... 5-5 5-3 Machine Check Syndrome Register (MCSR)......................................................................... 5-7 Freescale Semiconductor xiii
Page 1 and 2: e200z1 Power Architecture Core Refe
Page 3 and 4: Contents Paragraph Number Title Con
Page 5 and 6: Contents Paragraph Number Title e20
Page 11: Contents Paragraph Number Title e20
Page 15 and 16: Figures Figure Number Title e200z1
Page 17 and 18: Tables Table Number Title e200z1 Po
Page 19 and 20: Tables Table Number Title e200z1 Po
Page 21 and 22: Chapter 1 e200z1 Overview 1.1 Overv
Page 27 and 28: Chapter 2 Register Model This secti
Page 29 and 30: PSU Registers 1 PSU PSCR PSSR PSHR
Page 35 and 36: 17 (49) 18 (50) 19 (51) 20 (52) 21
Page 39 and 40: 8 (40) 9 (41) 10 (42) 11 (43) 12 (4
Page 43 and 44: 2.4.9 Timer Status Register (TSR) e
Page 45 and 46: 14 ICR Interrupt Inputs Clear Reser
Page 47 and 48: 2.4.13 Branch Unit Control and Stat
Page 49 and 50: Table 2-14. Additional Synchronizat
Page 51 and 52: Mnemonic Name Table 2-15. Special P
Page 53 and 54: Table 2-16. Reset Settings for e200
Page 55 and 56: Chapter 3 Instruction Model This ch
Page 57 and 58: 3.5 Memory Access Alignment Support
Page 63 and 64:
3.12.1 Instruction Index Sorted by
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Format Primary (Inst 0:5) Opcode e2
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Format Primary (Inst 0:5) Opcode X
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Format Primary (Inst 0:5) Opcode X
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Format Primary (Inst 0:5) Opcode XL
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Format Primary (Inst 0:5) Opcode Ta
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Format Primary (Inst0:5) Opcode Ext
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e200z1 Power Architecture Core Refe
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Chapter 4 Instruction Pipeline and
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4.1.2 Instruction Unit e200z1 Power
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Figure 4-2. Pipeline Diagram 4.3.1
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Time Slot 1st LD inst. IFETCH DEC /
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4.5.1 Completion Serialization e200
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4.7 Instruction Timings e200z1 Powe
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Chapter 5 Interrupts and Exceptions
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Interrupt Type e200z1 Power Archite
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14 (46) 15 (47) 16:23 (48:55) 5.3 M
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23 (55) 24 (56) 25 (57) 26 (58) 27
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MSR UCLE 0 WE 0 CE 0 EE 0 PR 0 ESR
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5.7.5 External Input Interrupt (IVO
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Table 5-18 lists register settings
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Table 5-21 lists register settings
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21 22 3 23 24 25 Data Storage 1. Ac
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Chapter 6 Memory Management Unit 6.
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21:25 [53:57] 26:27 [58:59] 28:29 [
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6.5 Software Interface and TLB Inst
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6.5.4 TLB Invalidate (tlbivax) Inst
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6.7.2 MMU Control and Status Regist
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Table 6-10. MAS1—Descriptor Conte
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The MAS3 register is shown in Figur
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6.7.4 MAS Registers Summary The MAS
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6.9 Core Interface Operation for MM
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Chapter 7 Core Complex Interfaces T
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Address Bus Transfer Control Transf
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Table 7-1. External Interface Signa
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j_lsrl_regsel O 0 External LSRL reg
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p_sprnum[0:9] O — Global SPR addr
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7.3.4.1 Transfer Type (p_d_htrans[1
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Table 7-8. p_[d,i]_hprot[5:0] Prote
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B. E. Word @001 0 0 1 1 0 0 B. E. W
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0 1 1 0 1 x x Reserved 0 1 1 1 0 x
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7.3.12.2 Processor Halt Request (p_
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7.3.14.1 OnCE Enable (jd_en_once) e
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1 j_tdo_en is asserted when the TAP
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7.3.15.14 Register Select (j_gp_reg
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Clock 2 (C2): e200z1 Power Architec
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7.4.1.5 Read and Write Transfers Fi
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7.4.1.6 Misaligned Accesses e200z1
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Figure 7-15 illustrates functional
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Figure 7-15 illustrates functional
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m_clk p_htrans p_addr,p_hprot p_hsi
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m_clk p_tbclk p_tbdisable t_tbclk_h
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Chapter 8 Power Management 8.1 Powe
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Chapter 9 Debug Support This chapte
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9.2.1 Instruction Address Compare E
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9.2.5 Branch Taken Debug Event e200
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9.2.13 Unconditional Debug Event e2
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Table 9-1 provides bit definitions
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9.3.3.2 Debug Control Register 1 (D
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9.3.3.3 Debug Control Register 2 (D
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Table 9-4. DBCR3 Bit Definitions (c
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posted, but the counter value will
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Table 9-9 indicates the e200 OnCE r
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Table 9-11 provides a list of acces
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9.4.7.4 Debug Request During Waitin
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9.4.8.2 Control State Register (CTL
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IRStat5—IR Status Bit 5 IRStat6
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To single-step the CPU: e200z1 Powe
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. 9.7.2 Parallel Signature Status R
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Appendix A Register Summary Conditi
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e200 z1 0 Figure A-3. e200 Supervis
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0 e200z1 Power Architecture Core Re
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* Figure A-27. CPU Scan Chain Regis
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M A S 0 M A S 1 M A S 2 M A S 3 M A
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Appendix B Revision History This ap
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Glossary The glossary contains an a
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Copy-back operation. A cache operat
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Local access window. Mapping used t
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Physical medium attachment (PMA) su
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Set (n). A subdivision of a cache.
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A Alignment exception, 5-15 B Branc
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