E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
– Critical Save/Restore register 1 (CSRR1). The CSRR1 register is used to save machine state
from the MSR on critical interrupts, and to restore machine state when rfci or se_rfci
executes.
— Debug facility registers
– Debug Control Registers (DBCR0-DBCR2). These registers provide control for enabling
and configuring debug events.
– Debug Status Register (DBSR). This register contains debug event status.
– Instruction Address Compare registers (IAC1-IAC4). These registers contain addresses
and/or masks which are used to specify Instruction Address Compare debug events.
– Data address compare registers (DAC1-2). These registers contain addresses and/or masks
which are used to specify Data Address Compare debug events.
– e200 does not implement the Data Value Compare registers (DVC1 and DVC2).
— Timer Registers
– Time base (TB). The TB is a 64-bit structure provided for maintaining the time of day and
operating interval timers. The TB consists of two 32-bit registers, Time Base Upper (TBU)
and Time Base Lower (TBL). The Time Base registers can be written to only by
supervisor-level software, but can be read by both user and supervisor-level software.
– Decrementer register (DEC). This register is a 32-bit decrementing counter that provides a
mechanism for causing a decrementer exception after a programmable delay.
– Decrementer Auto-Reload (DECAR). This register is provided to support the auto-reload
feature of the Decrementer.
– Timer Control Register (TCR). This register controls Decrementer, Fixed-Interval Timer,
and Watchdog Timer options.
– Timer Status Register (TSR). This register contains status on timer events and the most
recent Watchdog Timer-initiated processor reset.
2.2 e200-Specific Special Purpose Registers
The PowerPC Book E architecture allows implementation-specific special purpose registers. Those
incorporated in the e200 core are as follows:
User-level registers—The user-level registers can be accessed by all software with either user or
supervisor privileges. They include the following:
— The L1 Cache Configuration register (L1CFG0). This read-only register allows software to
query the configuration of the L1 Cache. For the e200z1, this register returns all zeros
indicating no cache is present.
Supervisor-level registers—The following supervisor-level registers are defined in e200 in
addition to the Power Architecture Book E registers described above:
— Configuration Registers
– Hardware implementation-dependent register 0 (HID0). This register controls various
processor and system functions.
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-6 Freescale Semiconductor