E200Z1RM, e200z1 Power Architecture Ž Core - Reference Manual

Register Model
2.4 Special Purpose Register Descriptions
2.4.1 Machine State Register (MSR)
The Machine State Register defines the state of the processor. Chapter 5, “Interrupts and Exceptions,”
describes how the MSR is affected when Interrupts occur. The e200 MSR is shown in Figure 2-4.
e200z1 0
UCLE
Allocated
The MSR bits are defined in Table 2-1.
0
WE
CE
e200z1 Power Architecture Core Reference Manual, Rev. 0
2-8 Freescale Semiconductor
0 EE
PR
FP
ME
FE0
0
DE
FE1
0 IS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Read/Write; Reset—0x0
Figure 2-4. Machine State Register (MSR)
Table 2-1. MSR Field Descriptions
Bit(s) Name Description
0:4
(32:36)
5
(37)
6
(38)
7:12
(39:44)
13
(45)
14
(46)
15
(47)
16
(48)
— Reserved 1
UCLE 2
User Cache Lock Enable
0 Execution of the cache locking instructions in user mode (MSR[PR]=1) disabled; DSI exception taken
instead, and ILK or DLK set in ESR.
1 Execution of the cache lock instructions in user mode enabled.
Allocated Allocated 3 - Allocated for SPE
Not supported on e200z1
— Reserved 1
WE Wait State (Power management) enable
0 Power management is disabled.
1 Power management is enabled. The processor can enter a power-saving mode when additional
conditions are present. The mode chosen is determined by the DOZE, NAP, and SLEEP bits in the
HID0 register, described in Section 2.4.11, “Hardware Implementation Dependent Register 0
(HID0).”
CE Critical Interrupt Enable
0 Critical Input and Watchdog Timer interrupts are disabled.
1 Critical Input and Watchdog Timer interrupts are enabled.
— Reserved 1
EE External Interrupt Enable
0 External Input, Decrementer, and Fixed-Interval Timer interrupts are disabled.
1 External Input, Decrementer, and Fixed-Interval Timer interrupts are enabled.
DS
0