Application Note AN-1150 - International Rectifier

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as mentioned earlier, for the PFC converter, the most important criterion for basing the selection of the compensation component values is the voltage loop bandwidth. Fig10: Voltage Loop error amplifier compensation network The error amplifier transfer function is given by: gm ⋅( 1+ sRgmCZ ) H 2 ( s ) = s( C + C + sR C C Z where g m is the transconductance of the voltage error amplifier. The compensation network adds a zero and a pole in the transfer function at: f f P0 Z 0 = π ⋅ P 1 2 R = 2π ⋅ R gm ⋅ C gm Z 1 Cz ⋅Cp Cz + Cp The gain and phase of the error amplifier + compensation transfer function is illustrated in Fig.11. gm Z P ) 90 60 30 0 EA Gain EA Phase 90 60 30 0 Gain (dB) -30 -60 -90 -120 -150 -30 -60 -90 -120 -150 Phase (deg) -180 -180 0.01 0.1 1 10 100 1000 10000 100000 f (Hz) Fig.11: Error Amplifier + compensation transfer function characteristics www.irf.com AN-1150 22
Voltage Loop Compensation procedure Step 1: Choose C z based on soft-start time: A soft-start time of 60ms is selected. Typical values range from 50ms to a few hundred ms, depending upon the application. The soft-start time represents the time needed by the controller to ramp V COMP from zero to the maximum value. The system will take no more than 60ms to achieve near-regulation. C Z = V t COMP SS ⋅ i OVEA ( EFF )( MIN ) i OVEA and V COMP(EFF) (MIN) are taken from the datasheet. 60ms × 44µ A C Z = = 0.56µ F 4.7V A standard value of 0.56uF can be selected for the converter for C Z . Step 2: Choose R gm to ensure that H 1 (s).H 2 (s) attenuation at 2xf AC frequency is small enough to avoid current distortion: The amount of 2xf AC ripple on the output capacitor is calculated first. The minimum f AC of 47Hz is considered here, since the ripple is the maximum at the lowest AC frequency. The peak-to-zero ripple V OPK is given by: V V V OPK OPK OPK P = 2π ⋅ 2 ⋅ f = 5.1V in, MAX AC ⋅ C O ⋅V out 380W = 2π ⋅ 2 ⋅ 47 ⋅ 330µ F ⋅385V The peak-to-peak ripple in V OUT is 2xV OPK . This ripple in V OUT is reflected in the V COMP voltage based on the attenuation provided by the resistor divider and error amplifier compensation network combined i.e. H 1 (s).H 2 (s) at 2xf AC . The ripple in V COMP i.e. ∆V COMP has to be small compared with the value of the error amplifier output voltage swing (V COMP,EFF ). Typical values for ∆V COMP /V COMP range from 0.5% to 1%. 0.5% is recommended if current shaping has to be excellent while 1% is recommended for higher phase margin and low-oscillation response to load steps. 0.5% attenuation demands a (G VA ) of: G VA V = COMP( EFF ) 2 ⋅V ⋅ 0.005 OPK www.irf.com AN-1150 23
Page 1 and 2: Application Note AN-1150 Power Fact
Page 3 and 4: • VFB - provides DC bus voltage s
Page 5 and 6: one of the comparator misbehaves, t
Page 7 and 8: 3.2 Power Circuit Design AC Line Br
Page 9 and 10: High Frequency Input Capacitor (C I
Page 11 and 12: V 4.7V ⋅ = 3.1 ( 1− 0.69) ISNS
Page 13 and 14: A standard 1MΩ, 1% tolerance resis
Page 15 and 16: 900mV V BOP 750mV ∆V BOP V BOP,AV
Page 17 and 18: at which the converter is expected
Page 19 and 20: i chg + Voltage loop compensation i
Page 21: Output voltage sensor Resistor-Divi
Page 25 and 26: 1 1 f P0 = ≅ Cz ⋅Cp 2π ⋅ R 2
Page 27 and 28: • Option 2: At the expense of cur
Page 29 and 30: to IC COM pin. However, in reality,
Page 31 and 32: 4.3 Pin ISNS Current sensing is alw

Application Note AN-1150 - International Rectifier

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