MAX9272 28-Bit GMSL Deserializer for Coax or STP Cable

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MAX9272 28-Bit GMSL Deserializer for Coax or STP Cable Pin Description (continued) PIN NAME FUNCTION 19 DOUT24/HS0 Parallel Data/Horizontal Sync 0 Output. Defaults to parallel data input on power-up. Parallel data output when VS/HS encoding is disabled. Decoded horizontal sync for lower half of single-output when VS/HS encoding is enabled (Table 2). 20, 41 IOVDD 21–40, 42–45 DOUT23– DOUT0 I/O Supply Voltage. 1.8V to 3.3V logic I/O power supply. Bypass IOVDD to EP with 0.1FF and 0.001FF capacitors as close as possible to the device with the smallest value capacitor closest to IOVDD. Parallel Data Outputs 46 PCLKOUT Parallel Clock Output. Latches parallel data into the input of another device. 47 MS/HVEN — EP Mode Select/HS and VS Encoding Enable with Internal Pulldown to EP. Function is determined by the state of LCCEN (Table 13). MS (LCCEN = high). Set MS = low to select base mode. Set MS = high to select the bypass mode. HVEN (LCCEN = low): Set HVEN = high to enable HS/VS encoding on DOUT_/HS_ and DOUT_/VS_. Set HVEN = low to use DOUT_/HS_ and DOUT_/VS_ as parallel data outputs. Exposed Pad. EP is internally connected to device ground. MUST connect EP to the PCB ground plane through an array of vias for proper thermal and electrical performance. Functional Diagram PCLKOUT SSPLL CLKDIV CDRPLL DOUT [23:0] DOUT24/HS0 DOUT25/ VS0 SERIAL TO PARALLEL IN+ IN- DOUT26/HS1 DOUT27/ VS1 VS /HS FIFO 1x[27:0] OR 2x[10:0] OR 2x[14:0] SCRAMBLE/ CRC/ HAMMING/ 8b/10b DECODE REVERSE CONTROL CHANNEL CML Rx AND EQ Tx GPIO0/DBL GPIO1/BWS GPI GPIO FCC UART/I 2 C MAX9272 TX/SCL/ES RX/SDA/EDC 14
MAX9272 28-Bit GMSL Deserializer for Coax or STP Cable IN+ R L /2 REVERSE CONTROL-CHANNEL TRANSMITTER IN- V OD R L /2 V CMR IN+ IN- V CMR IN- IN+ V ROH 0.9 x V ROH (IN+) - (IN-) 0.1 x V ROH 0.1 x V ROL tR 0.9 x V ROL tF V ROL Figure 1. Reverse Control-Channel Output Parameters 15
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MAX9272 28-Bit GMSL Deserializer for Coax or STP Cable

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