MAX9272 28-Bit GMSL Deserializer for Coax or STP Cable

MAX9272
28-Bit GMSL Deserializer for Coax or STP Cable
Table 16. Register Table (see Table 1) (continued)
REGISTER
ADDRESS
BITS NAME VALUE FUNCTION
DEFAULT
VALUE
0x06 D[7:0] — 00000010 Reserved. 00000010
D7
D6
D5
DBL
DRS
BWS
0
1
Single-input mode. Power-up default when LCCEN =
high or GPIO0/DBL = low.
Double-input mode. Power-up default when LCCEN =
low and GPIO0/DBL = high.
0 High data-rate mode.
1 Low data-rate mode.
0
1
24-bit mode. Power-up default when LCCEN = high or
GPIO1/BWS = low.
32-bit mode. Power-up default when LCCEN = low and
GPIO1/BWS = high.
0, 1
0
0, 1
0x07
D4
ES
0
1
Output data valid on rising edge of PCLKOUT.
Power-up default when LCCEN = high or TX/SCL/ES
= low. Do not change this value while the pixel clock is
running.
Output data valid on rising edge of PCLKOUT.
Power-up default when LCCEN = low and TX/SCL/ES
= high. Do not change this value while the pixel clock is
running.
0, 1
D3
HVTRACK
0
1
HS/VS tracking disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
HS/VS tracking enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
0, 1
D2
HVEN
0
1
HS/VS encoding disabled. Power-up default when
LCCEN = high or MS/HVEN = low.
HS/VS encoding enabled. Power-up default when
LCCEN = low and MS/HVEN = high.
0, 1
00
1-bit parity error detection (GMSL compatible).
Power-up default when LCCEN = high or RX/SDA/
EDC = low.
D[1:0]
EDC
01 6-bit CRC error detection.
10
6-bit hamming code (single-bit error correct, doublebit
error detect) and 16-word interleaving. Power-up
default when LCCEN = low and RX/SDA/EDC = high.
00, 10
11 Do not use.
42