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CS2013-final-report

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Table B-4: New and Expanded Core Learning Outcomes in <strong>CS2013</strong><br />

KA<br />

AL<br />

AR<br />

Core Learning Outcomes as described in <strong>CS2013</strong><br />

Core-Tier1:<br />

• Explain what is meant by “best”, “expected”, and “worst” case behavior of an<br />

algorithm.<br />

• In the context of specific algorithms, identify the characteristics of data and/or<br />

other conditions or assumptions that lead to different behaviors.<br />

• Perform empirical studies to validate hypotheses about runtime stemming from<br />

mathematical analysis. Run algorithms on input of various sizes and compare<br />

performance.<br />

• Give examples that illustrate time-space trade-offs of algorithms.<br />

• Use dynamic programming to solve an appropriate problem.<br />

• Explain how tree balance affects the efficiency of various binary search tree<br />

operations.<br />

Core-Tier2:<br />

• Define the classes P and NP.<br />

• Explain the significance of NP-completeness.<br />

• Discuss factors other than computational efficiency that influence the choice of<br />

algorithms, such as programming time, maintainability, and the use of<br />

application-specific patterns in the input data.<br />

Core-Tier2:<br />

• Comprehend the trend of modern computer architectures towards multi-core and<br />

that parallelism is inherent in all hardware systems.<br />

• Explain the implications of the “power wall” in terms of further processor<br />

performance improvements and the drive towards harnessing parallelism.<br />

• Design the basic building blocks of a computer: arithmetic-logic unit (gate-level),<br />

registers (gate-level), central processing unit (register transfer-level), and<br />

memory (register transfer-level).<br />

• Use CAD tools for capture, synthesis, and simulation to evaluate simple building<br />

blocks (e.g., arithmetic-logic unit, registers, movement between registers) of a<br />

simple computer design.<br />

• Evaluate the functional and timing diagram behavior of a simple processor<br />

implemented at the logic circuit level.<br />

• Compute Average Memory Access Time under a variety of cache and memory<br />

configurations and mixes of instruction and data references.<br />

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