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CS2013-final-report

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Body of Knowledge coverage<br />

KA Knowledge Unit Topics Covered Hours<br />

SF Processor architecture HLL constructs and Instruction-set design, datapath and control,<br />

microprogrammed implementation, example (MIPS)<br />

SF Program discontinuities Interrupts, traps, exceptions, nesting of interrupts, hardware for<br />

dealing with interrupts, interrupt handler code<br />

6<br />

2<br />

SF<br />

Processor performance<br />

metrics<br />

Space and time, memory footprint, execution time, instruction<br />

frequency, IPC, CPI, SPECratio, speedup, Amdahl’s law<br />

1<br />

SF Principles of pipelining Hardwired control, datapath of pipeline stages, pipeline registers,<br />

hazards (structural, data, and control) and solutions thereof<br />

(redundant hardware, register forwarding, branch prediction),<br />

example (Intel Core microarchitecture)<br />

SF Processor Scheduling Process context block, Types of schedulers (short-, medium-, longterm),<br />

preemptive vs. non-preemptive schedulers, short-term<br />

scheduling algorithms (FCFS, SJF, SRTF, priority, round robin),<br />

example (Linux O(1) scheduler)<br />

5<br />

2<br />

SF<br />

Scheduling performance<br />

metrics<br />

CPU utilization, throughput, response time, average response<br />

time/waiting time, variance in response time, starvation<br />

1<br />

SF Memory management Process address space, static and dynamic relocation, memory<br />

allocation schemes (fixed and variable size partitions), paging,<br />

segmentation<br />

2<br />

SF<br />

Page-based memory<br />

management<br />

Demand paging, hardware support (page tables, TLB), interaction<br />

with processor scheduling, OS data structures, page replacement<br />

algorithms (Belady’s Min, FIFO, LRU, clock), thrashing, working<br />

set, paging daemon<br />

2<br />

SF Processor caches Spatial and temporal locality, cache organization (direct mapped,<br />

fully associative, set associative), interaction with virtual memory,<br />

virtually indexed physically tagged caches, page coloring<br />

3<br />

SF Main memory DRAM, page mode DRAM, Memory buses 0.5<br />

SF<br />

Memory system<br />

performance metrics<br />

Context switch overhead, page fault service time, memory pressure,<br />

effective memory access time, memory stalls<br />

0.5<br />

SF Parallel programming Programming with pthreads, synchronization constructs (mutex<br />

locks and condition variables), data races, deadlock and livelock,<br />

program invariants<br />

3<br />

SF<br />

OS support for parallel<br />

programming<br />

Thread control block, thread vs. process, user level threads, kernel<br />

level threads, scheduling threads, TLB consistency<br />

1.5<br />

SF<br />

Architecture support for<br />

parallel programming<br />

Symmetric multiprocessors (SMP), atomic RMW primitives, T&S<br />

instruction, bus-based cache consistency protocols<br />

1.5<br />

- 416 -

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