CS2013-final-report

CS150: Digital Components and Design, University of California,
Berkeley
Randy H. Katz
randy@cs.Berkeley.edu
http://inst.eecs.berkeley.edu/~cs150/
Knowledge Areas that contain topics and learning outcomes covered in the course
Knowledge Area
Total Hours of Coverage
Architecture and Organization (AR) 37.5
Where does the course fit in your curriculum
This is a junior-level course in the computer science curriculum for computer engineering students interested in
digital system design and implementation.
What is covered in the course
Design of synchronous digital systems using modern tools and methodologies, in particular, digital logic synthesis
tools, digital hardware simulation tools, and field programmable gate array architectures.
What is the format of the course
Lecture, discussion section, laboratory
How are students assessed
Laboratories, examinations, and an independent design project
Course textbook and materials
Harris and Harris, Digital Design and Computer Architecture
Why do you teach the course this way
Understand the principles and methodology of digital logic design at the gate and switch level, including both
combinational and sequential logic elements. Gain experience developing a relatively large and complex digital
system. Gain experience with modern computer-aided design tools for digital logic design. Understand clocking
methodologies used to control the flow of information and manage circuit state. Appreciate methods for specifying
digital logic, as well as the process by which a high-level specification of a circuit is synthesized into logic
networks. Appreciate the tradeoffs between hardware and software implementations of a given function.
Appreciate the uses and capabilities of a modern FPGA platform.
Body of Knowledge coverage
KA Knowledge Unit Topics Covered Hours
AR Digital Logic and Digital Systems Combinational /Sequential
Logic Design and CAD Tools;
State Machines, Counters;
Digital Building Blocks;
High Level Design w/Verilog
4.5
4.5
3
4.5
4.5
AR Machine Level Representation of Data N/A 0
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