Xilinx UG002 Virtex-II Platform FPGA User Guide

Product Obsolete/Under ObsolescenceRIntroduction ............................................................................................................. 249Creating an LVPECL Input/Clock Buffer ................................................................. 249Creating an LVPECL Output Buffer ......................................................................... 250Using Bitstream Encryption ........................................................................................... 252What DES Is ............................................................................................................. 252How Triple DES is Different ..................................................................................... 252Classification and Export Considerations ................................................................. 253Creating Keys ........................................................................................................... 253Loading Keys ........................................................................................................... 255Loading Encrypted Bitstreams .................................................................................. 255V BATT ........................................................................................................................................................ 255Temperature-Sensing Diode (DXP/DXN) ................................................................. 255Using the CORE Generator System.............................................................................. 257Introduction ............................................................................................................. 257The CORE Generator System .................................................................................... 257CORE Generator Design Flow .................................................................................. 258Core Types ............................................................................................................... 259Xilinx IP Solutions and the IP Center ........................................................................ 261CORE Generator Summary ...................................................................................... 263Virtex-II IP Cores Support ........................................................................................ 263Chapter 4: ConfigurationSummary ............................................................................................................................ 273Introduction....................................................................................................................... 273Configuration Modes ............................................................................................... 274Configuration Process and Flow ............................................................................... 276Configuration Pins ................................................................................................... 280Mixed Voltage Environments ................................................................................... 281Configuration Solutions ................................................................................................. 282Configuration PROMs .............................................................................................. 282Flash PROMs With a CPLD Configuration Controller ............................................... 283Embedded Solutions ................................................................................................ 284Software Support and Data Files .................................................................................. 285iMPACT Software .................................................................................................... 285Programming Cables ................................................................................................ 285Boundary Scan Interconnect Testing for Virtex-II Devices ......................................... 285In-System Programming Data Files .......................................................................... 285Serial Programming Modes............................................................................................ 286Master Serial Mode .................................................................................................. 286Slave Serial Mode ..................................................................................................... 287SelectMAP Programming Modes.................................................................................. 289Master SelectMAP Mode .......................................................................................... 291Slave SelectMAP Mode ............................................................................................ 292SelectMAP ABORT Sequence and ABORT Recovery.............................................. 297Triggering an ABORT .............................................................................................. 297ABORT Status Word ................................................................................................ 298ABORT Recovery ..................................................................................................... 299Internal Configuration Access Port (ICAP)................................................................. 30010 www.xilinx.com UG002 (v2.2) 5 November 20071-800-255-7778 Virtex-II Platform FPGA User Guide