Xilinx UG002 Virtex-II Platform FPGA User Guide

Product Obsolete/Under ObsolescenceDate Version Revision02/04/04(cont’d)1.7(cont’d)• The following parameter specification tables were removed from Chapter 4,Configuration (formerly Chapter 3):- Table 3-3, Power-Up Timing Configuration Signals- Table 3-7, Master/Slave Serial Mode Programming Switching- Table 3-8, SelectMAP Write Timing Characteristics- Table 3-12, Boundary-Scan Port Timing SpecificationsSee the Virtex-II Platform FPGA Data Sheet, DC and Switching Characteristics forthese and all other parameter specifications.• Section "Mixed Voltage Environments" on page 281: Restructured with newheadings. Reworded Footnote (1) in Figure 4-4.• Added footnote to Figure 4-8 on page 286 and Figure 4-10 on page 288 clarifying thatDOUT transitions on the falling edge of CCLK.• Second paragraph below Figure 4-12 on page 292: Corrected maximumno-handshake SelectMAP configuration speed from 5 MHz to 50 MHz.• Section "Master SelectMAP Data Loading" on page 292: Changed wording toemphasize that if RDWR_B is toggled while CS_B is still asserted, a configurationabort will occur.• Section "Express-Style Loading" on page 286: Added new text to clarify thesequencing of signals before, during, and after data loading.• Section "Test Access Port" on page 301: Added mention of implementation tool pullup,pull-down, and float options on TMS and TDI pins.• Table 4-12 on page 309: Updated XC2V8000 configuration bitstream length.• Table 5-3 on page 423: Changed Theta-JC to 0.5°C/Watt for all FF packages.04/16/04 1.8 • End of Table 3-37 on page 192, added reference to XAPP689 for detailed groundbounce discussion.• Section "DCI I/O Buffer Library Components" on page 217, deletedIBUF_LVDS_33_DCI, IBUFG_LVDS_33_DCI, IBUF_LVDSEXT_33_DCI, andIBUFG_LVDSEXT_33_DCI.• Section "DCI in Virtex-II Hardware" on page 221, deleted LVDS_33_DCI andLVDSEXT_33_DCI.• Section "Using Bitstream Encryption" on page 252, added reference to Appendix C,Choosing the Battery for V BATT .• End of section "Creating Keys" on page 253, added paragraph advising use of adifferent CBC initial value for each design to insure security.• Table 4-3 on page 280, added instruction to connect V BATT to V CCAUX or GND whenbitstream encryption is not used.• Section "Frame Length Register (FLR)" on page 310, corrected definition of the valueloaded into this register by adding “minus one word.”Virtex-II Platform FPGA User Guide www.xilinx.com UG002 (v2.2) 5 November 2007