Xilinx UG002 Virtex-II Platform FPGA User Guide

Pin-to-Pin Timing ModelProduct Obsolete/Under ObsolescenceRGlobal Clock Setup and HoldFigure 2-24 illustrates the paths associated with the timing parameters defined in thissection. Note, they differ only in their use of the DCM.Global Clock PinIOBBUFGMUXQDInputPinIOBInputPinDQDCMBUFGMUXGlobal Clock PinUG002_C3_014_101300Figure 2-24:Global Clock Setup and Hold ModelTiming ParametersSetup and Hold for Input Registers Relative to the Global Clock (pin):• T PSDLL / T PHDLL - Time before the Global Clock (pin), with DCM, that the inputsignal must be stable at the D-input of the IOB input register.• T PSFD / T PHFD - Time before the Global Clock (pin), without DCM, that the inputsignal must be stable at the D-input of the IOB input register.Note: T PSFD = Setup time (before clock edge) and T PHFD = Hold time (after clock edge). Theprevious descriptions are for setup times only.UG002 (v2.2) 5 November 2007 www.xilinx.com 51Virtex-II Platform FPGA User Guide