Xilinx UG002 Virtex-II Platform FPGA User Guide

RProduct Obsolete/Under ObsolescenceChapter 2: Timing ModelsTiming ParametersTable 2-2:Slice Distributed RAM Timing ParametersParameterFunctionControlSignalDescriptionSequential Delays for Slice LUT Configured as RAM (Distributed RAM)T SHCKO16T SHCKO32T SHCKOF5CLK to X/Y outputs(WE active) in 16x1modeCLK to X/Y outputs(WE active) in 32x1modeCLK to F5 output (WEactive)Time after the Clock (CLK) of a WRITEoperation that the data written to thedistributed RAM (in 16x1 mode) is stable onthe X/Y outputs of the slice.Time after the Clock (CLK) of a WRITEoperation that the data written to thedistributed RAM (in 32x1 mode) is stable onthe X/Y outputs of the slice.Time after the Clock (CLK) of a WRITEoperation that the data written to thedistributed RAM is stable on the F5 output ofthe slice.Setup and Hold for Slice LUT Configured as RAM (Distributed RAM)T xS = Setup time (before clock edge)T xH = Hold time (after clock edge)T DS /T DHBX/BY Data inputs(DI)The following descriptions are for setuptimes only.Time before the clock that data must be stableat the DI input of the slice LUT (configured asRAM), via the slice BX/BY inputs.T AS /T AHT WES /T WEHClock CLKT WPHT WPLT WCF/G Address inputsWE input (SR)Time before the clock that address signalsmust be stable at the F/G inputs of the sliceLUT (configured as RAM).Time before the clock that the Write Enablesignal must be stable at the WE input of theslice LUT (configured as RAM).Minimum Pulse Width, High (for aDistributed RAM clock).Minimum Pulse Width, Low (for aDistributed RAM clock).Minimum clock period to meet address writecycle time.26 www.xilinx.com UG002 (v2.2) 5 November 2007Virtex-II Platform FPGA User Guide