Xilinx UG002 Virtex-II Platform FPGA User Guide

Pin-to-Pin Timing ModelProduct Obsolete/Under ObsolescenceRGlobal Clock Input to OutputFigure 2-22 illustrates the paths associated with the timing parameters defined in thissection. Note that they differ only in their use of the DCM.Global Clock PinBUFGMUXDataIOB OutputRegisterDQOutputPinOutputPinIOB OutputRegisterQDDataDCMBUFGMUXGlobal Clock PinUG002_C3_013_101300Figure 2-22:Global Clock Input to Output ModelTiming ParametersTable 2-8:Global Clock Input to Output Timing ParametersParameterT ICKOFDLLT ICKOFDescriptionTime after the Global Clock (pin), using the DCM, that the output datafrom an IOB Output flip-flop is stable at the output pin.Time after the Global Clock (pin), without the DCM, that the output datafrom an IOB Output flip-flop is stable at the output pin.UG002 (v2.2) 5 November 2007 www.xilinx.com 49Virtex-II Platform FPGA User Guide