Xilinx UG002 Virtex-II Platform FPGA User Guide

IOB Timing ModelProduct Obsolete/Under ObsolescenceRTable 2-7:ParameterSetup and Hold With Respect to Clock at IOB 3-State RegisterT xxCK = Setup time (before clock edge)T xxCKxx = Hold time (after clock edge)T IOTCK /T IOCKTIOB 3-State Timing Parameters (Continued)FunctionT inputControlSignalDescriptionThe followingdescriptions are for setuptimes only.Time before the clock that thesignal must be stable at the Tinput of the IOB 3-stateRegister.T IOTCECK /T IOCKTCETCE inputTime before the clock that theclock enable signal must bestable at the TCE input of theIOB 3-state Register.T IOSRCKT /T IOCKTSR SR input (TFF)Time before the clock that theset/reset signal.Clock to OutT IOCKHZT IOCKONSet/Reset DelaysT IOSRHZT IOSRONClock (CLK) to pad High-ZClock (CLK) to valid data onpadSR Input to pad High-Z(asynchronous)SR Input to valid data on pad(asynchronous)Time after clock that the padgoes to high-impedance.Time after clock that the padgoes from high-impedance tovalid data.Time after the SR signal istoggled that the pad goes tohigh-impedance.Time after the SR signal istoggled that the pad goesfrom high-impedance to validdata.UG002 (v2.2) 5 November 2007 www.xilinx.com 45Virtex-II Platform FPGA User Guide