Xilinx UG002 Virtex-II Platform FPGA User Guide

Block SelectRAM Timing ModelProduct Obsolete/Under ObsolescenceRClock Event 4: SSR (Synchronous Set/Reset) OperationDuring an SSR operation, initialization parameter value SRVAL is loaded into the outputlatches of the block SelectRAM. The SSR operation does NOT change the contents of thememory and is independent of the ADDR and DI inputs.• At time T BRCK before Clock Event 4, the synchronous set/reset signal becomes valid(High) at the SSR input of the block RAM.• At time T BCKO after Clock Event 4, the SRVAL 0101 becomes valid at the DO outputsof the block RAM.Clock Event 5: Disable OperationDe-asserting the enable signal EN disables any write, read or SSR operation. The disableoperation does NOT change the contents of the memory or the values of the output latches.• At time T BECK before Clock Event 5, the enable signal becomes valid (Low) at the ENinput of the block RAM.• After Clock Event 5, the data on the DO outputs of the block RAM is unchanged.Timing ModelFigure 2-9 illustrates the delay paths associated with the implementation of blockSelectRAM. This example takes the simplest paths on and off chip (these paths can varygreatly depending on the design). This timing model demonstrates how and where theblock SelectRAM timing parameters are used.FPGABlock SelectRAMDataAddressWrite EnableEnableSynchronousSet/Reset[T IOPI + NET] + T BDCK[T IOPI + NET] + T BACK[T IOPI + NET*] + T BWCK[T IOPI + NET] + T BECK[T IOPI + NET] + T BRCKDIADDRWEENSSRCLKDOT BCKO + [NET + T IOOP ]Data[T GI0O + NET]BUFGMUXClock[T IOPI + NET]ug002_c3_003_101300Figure 2-9:Block SelectRAM Timing ModelNET = Varying interconnect delaysT IOPI = Pad to I-output of IOB delayT IOOP = O-input of IOB to pad delayT GI0O = BUFGMUX delayUG002 (v2.2) 5 November 2007 www.xilinx.com 33Virtex-II Platform FPGA User Guide