Xilinx UG002 Virtex-II Platform FPGA User Guide

CLB / Slice Timing ModelProduct Obsolete/Under ObsolescenceRTiming ParametersTable 2-3:ParameterSlice SRL Timing ParametersFunctionControlSignalDescriptionSequential Delays for Slice LUT Configured as SRL (Select Shift Register)T REGT CKSHT REGF5CLK toX/Y outputsCLK to ShiftoutCLK to F5 outputTime after the Clock (CLK) of a WRITE operationthat the data written to the SRL is stable on theX/Y outputs of the slice.Time after the Clock (CLK) of a WRITE operationthat the data written to the SRL is stable on theShiftout or XB/YB outputs of the slice.Time after the Clock (CLK) of a WRITE operationthat the data written to the SRL is stable on the F5output of the slice.Setup/Hold for Slice LUT Configured as SRL (Select Shift Register)T xxS = Setup time (before clock edge)T xxH = Hold time (after clock edge)T SRLDS /T SRLDHBX/BY Data inputs(DI)The following descriptions are for setup timesonly.Time before the clock that data must be stable atthe DI input of the slice LUT (configured as SRL),via the slice BX/BY inputs.T WSS /T WSHClock CLKT SRPHT SRPLCE input (WE)Time before the clock that the Write Enable signalmust be stable at the WE input of the slice LUT(configured as SRL).Minimum Pulse Width, High (for an SRL clock).Minimum Pulse Width, Low (for an SRL clock).Timing CharacteristicsFigure 2-6 illustrates the timing characteristics of a 16-bit shift register implemented in aVirtex-II slice (LUT configured as SRL).1 2 3 4 5 6TSRPHCLKWrite Enable(SR)Shift_In (DI)TSRPLTWSSTSRLDS01 1 0 1 0Address02 1TREGTILOTILOData Out (D) X0 1 1 01 1 0 1TREGXBMSB (MC15) X X X X X X X160Figure 2-6:Slice SLR Timing DiagramUG002_C3_022_102700UG002 (v2.2) 5 November 2007 www.xilinx.com 29Virtex-II Platform FPGA User Guide