Xilinx UG002 Virtex-II Platform FPGA User Guide

IOB Timing ModelProduct Obsolete/Under ObsolescenceRTiming CharacteristicsFigure 2-14 illustrates IOB input register timing.1 2 3 4 5CLKTIOPICKITIOICECKICESR(reset)IQTIOCKIQTIOSRCKITIOCKIQFigure 2-14:IOB Input Register Timing DiagramUG002_c3_005_112700Clock Event 1• At time T IOICECK before Clock Event 1, the input clock enable signal becomes valid-highat the ICE input of the input register, enabling the input register for incoming data.• At time T IOPICK before Clock Event 1, the input signal becomes valid-high at the Iinput of the input register and is reflected on the IQ output of the input register attime T IOCKIQ after Clock Event 1.Clock Event 4• At time T IOSRCKI before Clock Event 4 the SR signal (configured as synchronous resetin this case) becomes valid-high resetting the input register and reflected at the IQoutput of the IOB at time T IOCKIQ after Clock Event 4.UG002 (v2.2) 5 November 2007 www.xilinx.com 39Virtex-II Platform FPGA User Guide