Xilinx UG002 Virtex-II Platform FPGA User Guide

Embedded Multiplier Timing ModelProduct Obsolete/Under ObsolescenceRTiming CharacteristicsFigure 2-12 illustrates the result (outputs) of a 4-bit x 4-bit unsigned multiply implementedin an embedded multiplier block.Time 0input[3..0]1111input[3..0]1111T MULT (P0)P0X1T MULT (P1)P1X0P2TMULT (P2)XTMULT (P3)0P3XTMULT (P4)0P4XTMULT (P5)0P5XTMULT (P6)1P6XTMULT (P7)1P7X1Figure 2-12:Embedded Multiplier Block Timing DiagramUG002_C3_024_101300At time 0 the two 4-bit numbers to be multiplied become valid at the A[0..3], B[0..3] inputsto the embedded multiplier. The result appears on the output pins P[0..7] in a staggeredfashion. First, P0 becomes valid at time T MULT (P0), followed by each subsequent outputpin, until P7 becomes valid at time T MULT (P7). In this case, the delay for this multiplyfunction should correspond to that of Pin 7. In other words, the result is not valid until alloutput pins become valid.UG002 (v2.2) 5 November 2007 www.xilinx.com 35Virtex-II Platform FPGA User Guide