Xilinx UG002 Virtex-II Platform FPGA User Guide

IOB Timing ModelProduct Obsolete/Under ObsolescenceIOB Input Timing Model and ParametersFigure 2-13 illustrates IOB inputs.RPADID1FFLATCHQ1IQ1ICLK1CESRREVICED2FFLATCHQ2IQ2CEICLK2SRREVSRREVUG002_C3_004_101300Figure 2-13:Virtex-II IOB Input DiagramTiming ParametersTable 2-5:ParameterIOB Input Timing ParametersFunctionControlSignalDescriptionPropagation DelaysT IOPIT IOPIDT IOPLIT IOPLIDPropagation delay from the pad to Ioutput of the IOB with no delay adder.Propagation delay from the pad to Ioutput of the IOB with the delay adder.Propagation delay from the pad to IQoutput of the IOB via transparent latchwith no delay adder.Propagation delay from the pad to IQoutput of the IOB via transparent latchwith the delay adder.UG002 (v2.2) 5 November 2007 www.xilinx.com 37Virtex-II Platform FPGA User Guide