Xilinx UG002 Virtex-II Platform FPGA User Guide

IOB Timing ModelProduct Obsolete/Under ObsolescenceIOB Output Timing Model and ParametersFigure 2-16 illustrates IOB outputs.RO1Sharedby allregistersOCEOTCLK1SRREVD1FFLATCHQ1CECK1SR REVAttribute INIT1INIT0SRHIGHSRLOWFF1DDR MUXFF2OQ3-StateControlPADFFLATCHD2Q2OTCLK2O2CECK2SR REVAttributeINIT1INIT0SRHIGHSRLOWReset TypeSYNCASYNCUG002_C3_007_101300Figure 2-16:Virtex-II IOB Output DiagramTiming ParametersTable 2-6:ParameterIOB Output Timing ParametersFunctionControlSignalDescriptionPropagation DelaysT IOOPT IOOLPPropagation delay from the O input of theIOB to the pad.Propagation delay from the O input of theIOB to the pad via transparent latch.Setup and Hold With Respect to Clock at IOB Output RegisterT xxCK = Setup time (before clock edge)T xxCKxx = Hold time (after clock edge)The following descriptions are for setup timesonly.T IOOCK /T IOCKOT IOOCECK /T IOCKOCET IOSRCKO /T IOCKOSRO inputOCE inputSR input (OFF)Time before the clock that data must bestable at the O input of the IOB OutputRegister.Time before the clock that the ClockEnable signal must be stable at the OCEinput of the IOB Output Register.Time before the clock that the Set/Resetsignal must be stable at the SR input of theIOB Output Register.UG002 (v2.2) 5 November 2007 www.xilinx.com 41Virtex-II Platform FPGA User Guide