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Xilinx UG002 Virtex-II Platform FPGA User Guide

Xilinx UG002 Virtex-II Platform FPGA User Guide

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RProduct Obsolete/Under ObsolescencePreface: About This <strong>Guide</strong>ResourceTech TipsAnswersDatabaseDescription/URLSee this site for the latest news, design tips, and patch information on the<strong>Xilinx</strong> design environment.http://www.xilinx.com/support/techsup/journals/index.htmThis database provides a current listing of solution records for <strong>Xilinx</strong>software tools. Search this database using the search function at:http://www.xilinx.com/support/searchtd.htmConventionsThis document uses the following conventions. An example illustrates each convention.TypographicalThe following typographical conventions are used in this document:Convention Meaning or Use ExampleCourier fontCourier boldHelvetica boldItalic fontSquare brackets [ ]Braces { }Vertical bar |Messages, prompts, andprogram files that the systemdisplaysLiteral commands that youenter in a syntactical statementCommands that you selectfrom a menuKeyboard shortcutsVariables in a syntaxstatement for which you mustsupply values. (In anglebrackets.)References to other manualsEmphasis in textAn optional entry orparameter. However, in busspecifications, such asbus[7:0], they are required.A list of items from which youmust choose one or moreSeparates items in a list ofchoicesspeed grade: - 100ngdbuild design_nameFile → OpenCtrl+Cngdbuild See the Development SystemReference <strong>Guide</strong> for moreinformation.If a wire is drawn so that itoverlaps the pin of a symbol,the two nets are not connected.ngdbuild [option_name]design_namelowpwr ={on|off}lowpwr ={on|off}16 www.xilinx.com <strong>UG002</strong> (v2.2) 5 November 2007<strong>Virtex</strong>-<strong>II</strong> <strong>Platform</strong> <strong>FPGA</strong> <strong>User</strong> <strong>Guide</strong>

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