Xilinx UG002 Virtex-II Platform FPGA User Guide

Product Obsolete/Under ObsolescenceRLocation Constraints .................................................................................................. 75Secondary Clock Network .......................................................................................... 75VHDL and Verilog Instantiation ................................................................................. 75Using Digital Clock Managers (DCMs)......................................................................... 80Overview ................................................................................................................... 80Clock De-Skew ........................................................................................................... 81Frequency Synthesis ................................................................................................... 90Phase Shifting ............................................................................................................ 94DCM Waveforms ..................................................................................................... 110Using Block SelectRAM Memory ............................................................................. 113Introduction ............................................................................................................. 113Synchronous Dual-Port and Single-Port RAM .......................................................... 113Characteristics .......................................................................................................... 117Library Primitives .................................................................................................... 117VHDL and Verilog Instantiation ............................................................................... 119Port Signals .............................................................................................................. 119Address Mapping .................................................................................................... 120Attributes ................................................................................................................. 121Initialization in VHDL or Verilog Codes ................................................................... 122Location Constraints ................................................................................................ 122Applications ............................................................................................................. 123VHDL and Verilog Templates .................................................................................. 123Using Distributed SelectRAM Memory ...................................................................... 130Introduction ............................................................................................................. 130Characteristics .......................................................................................................... 131Library Primitives .................................................................................................... 132VHDL and Verilog Instantiation ............................................................................... 133Ports Signals ............................................................................................................ 133Attributes ................................................................................................................. 133Initialization in VHDL or Verilog Codes ................................................................... 134Location Constraints ................................................................................................ 134Applications ............................................................................................................. 136VHDL and Verilog Templates .................................................................................. 137Using Look-Up Tables as Shift Registers (SRLs)....................................................... 140Introduction ............................................................................................................. 140Shift Register Operations .......................................................................................... 140Characteristics .......................................................................................................... 142Library Primitives and Submodules ......................................................................... 142Initialization in VHDL and Verilog Code .................................................................. 145Port Signals .............................................................................................................. 145Attributes ................................................................................................................. 145Location Constraints ................................................................................................ 146Fully Synchronous Shift Registers ............................................................................ 147Static-Length Shift Registers ..................................................................................... 148VHDL and Verilog Instantiation ............................................................................... 149Designing Large Multiplexers ....................................................................................... 151Introduction ............................................................................................................. 151Virtex-II CLB Resources ........................................................................................... 151Wide-Input Multiplexers .......................................................................................... 155Characteristics .......................................................................................................... 155Library Primitives and Submodules ......................................................................... 1568 www.xilinx.com UG002 (v2.2) 5 November 20071-800-255-7778 Virtex-II Platform FPGA User Guide