Xilinx UG002 Virtex-II Platform FPGA User Guide

Block SelectRAM Timing ModelProduct Obsolete/Under ObsolescenceRDIDIPADDRWEENSSRCLKDODOPDS031_10_071602Figure 2-7:Block SelectRAM Block DiagramTiming ParametersTable 2-4:ParameterBlock SelectRAM Timing ParametersFunctionControlSignalDescriptionSetup and Hold Relative to Clock (CLK)T BxCK = Setup time (before clock edge)T BCKx = Hold time (after clock edge)T BACK /T BCKA Address inputs ADDRT BDCK /T BCKD Data inputs DIT BECK /T BCKE Enable ENThe following descriptions are for setup times only.Time before the clock that address signals mustbe stable at the ADDR inputs of the block RAM.Time before the clock that data must be stable atthe DI inputs of the block RAM.Time before the clock that the enable signal mustbe stable at the EN input of the block RAM.T BRCK /T BCKRSynchronousSet/ResetSSRTime before the clock that the synchronousset/reset signal must be stable at the SSR input ofthe block RAM.T BWCK /T BCKW Write Enable WETime before the clock that the write enable signalmust be stable at the WE input of the block RAM.Clock to OutT BCKOClock to OutputCLK toDOTime after the clock that the output data is stableat the DO outputs of the block RAM.ClockT BPWH Clock CLK Minimum pulse width, high.T BPWL Clock CLK Minimum pulse width, low.UG002 (v2.2) 5 November 2007 www.xilinx.com 31Virtex-II Platform FPGA User Guide