Xilinx UG002 Virtex-II Platform FPGA User Guide

RCLB / Slice Timing ModelIntroductionProduct Obsolete/Under ObsolescenceChapter 2: Timing ModelsThe three sections below describes all timing parameters reported in the Virtex-II DataSheet that are associated with slices and Configurable Logic Blocks (CLBs). The sectionscorrespond to their respective (switching characteristics) sections in the data sheet:• General Slice Timing Model and Parameters (CLB Switching Characteristics)• Slice Distributed RAM Timing Model and Parameters (CLB Distributed RAMSwitching Characteristics)• Slice SRL Timing Model and Parameters (CLB SRL Switching Characteristics)General Slice Timing Model and ParametersFigure 2-1 illustrates the details of a Virtex-II slice.Note: Some elements of the Virtex-II slice have been omitted for clarity. Only the elementsrelevant to the timing paths described in this section are shown.FXINAFXINBMUXFXFXYDYGinputsLUTDD QFF/LATCECLKYQSRREVBYMUXF5F5XLUTFinputsDDXD QFF/LATCECLKXQSRREVBXCECLKSRUG002_C3_017_113000Figure 2-1:General Slice Diagram22 www.xilinx.com UG002 (v2.2) 5 November 2007Virtex-II Platform FPGA User Guide