SoC Encounter for Designers II - Integrated Systems Laboratory

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Student Task 3:• Now, for this exercise you can start with the almost complete I/O file src/chip.io−incomplete\instead of the template file. This file has all the pads placed properly with the exception ofthe 16 pads of the input bus DataInxDI which are still missing.Furthermore the file src/filter chip.sequence.io mentioned above has already been generatedfor you.The desired I/O assignment is depicted in the figure below and can also be found in the filesrc/filter chip.io.ps a .• Create the complete I/O file and save it as src/filter chip.io.aPostscript viewers were very common in the earlier days, you can use gv, kghostview, or evince to view this fileYou can use the utility src/io2ps.pl to generate a postscript file from your I/O file. This utility will alsoverify if you have used the correct offset locations in you I/O file, and will report errors. For bestresults, you should also provide the Verilog netlist file, which will enable the script to make even morechecks.sh >./io2ps.pl filter_chip.io > filter_chip.pin_diagram.psThe src/io2ps.pl utility uses a configuration file with the extension .pads. Per default the file src/io2ps\.pads will be used. If you are planning to use the extended power scheme, you will have to add theconfiguration file src/io2ps−ep.pads to the command as well.pad_vcc_p11565554535251504948474645444342pad_gnd_p3DataInxDI_PAD_9241DataOutxDO_PAD_11DataInxDI_PAD_8340DataOutxDO_PAD_10DataInxDI_PAD_7439DataOutxDO_PAD_9DataInxDI_PAD_6538DataOutxDO_PAD_8DataInxDI_PAD_5637DataOutxDO_PAD_7pad_gnd_c1736pad_vcc_c3pad_vcc_c1835pad_gnd_c3DataInxDI_PAD_4934DataOutxDO_PAD_6DataInxDI_PAD_31033DataOutxDO_PAD_5DataInxDI_PAD_21132DataOutxDO_PAD_4DataInxDI_PAD_11231DataOutxDO_PAD_3DataInxDI_PAD_01330DataOutxDO_PAD_2pad_gnd_p114151617181920212223242526272829pad_vcc_p3pad_vcc_p2DataInxDI_PAD_10DataInxDI_PAD_11DataInxDI_PAD_12DataInxDI_PAD_13DataInxDI_PAD_14pad_gnd_c2pad_vcc_c2DataInxDI_PAD_15DataOutAckxSI_PADDataOutReqxSO_PADDataOutxDO_PAD_0DataOutxDO_PAD_1pad_gnd_p2pad_gnd_p4DataOutxDO_PAD_12DataOutxDO_PAD_13DataOutxDO_PAD_14DataOutxDO_PAD_15ResetxRBI_PADpad_vcc_c4pad_gnd_c4ClkxCI_PADScanEnxTI_PADRamTestxTI_PADDataInAckxSO_PADDataInReqxSI_PADpad_vcc_p410
3.2.3 Timing ConstraintsJust as for synthesis, we need to specify timing constraints for the backend design with CADENCESOC ENCOUNTER .With decreasing process geometries the impact of placement and routing on timing, power, etc. issteadily increasing. Therefore, timing analysis and optimization have become very important in orderto arrive at a layout that (still) satisfies all requirements.As CADENCE SOC ENCOUNTER supports most of the more common SYNOPSYS DESIGN COMPILERcommands/constraints it should be rather straight forward to create an appropriate timing constraintsfile based on the constraints used for synthesis.Student Task 4:• There is an example constraint file src/sample/chip.sdc−sample that contains the mostcommonly used commands along with many useful and important comments.Copy this file to src/chip.sdc and modify it so that the following constraints get set (andnothing else!):– Define a 125 MHz clock– Specify 3.5 ns input delay for all inputs– Specify 5.0 ns output delay for all outputs– Specify an input transition time of 0.8 ns at all inputs– Specify a 15 pF output load for all outputs3.2.4 Technology FilesThe tech directory and the two subdirectories contain technology files that describe the technologyitself as well as libraries of standard building blocks implemented in this technology, i.e. standardcells, pads, RAM/ROM.• Technology files (UMCL180)lef/header6 V55.lef Base technology description, defines metal layers, vias, spacing rules,routingumcL180.capTbl Table used to extract parasitic capacitances and resistances for signal andpower wires.streamout.map Layer mapping table used when exporting the final layout in GDSII format.• Library files (standard cells, pads, macro-cells)lef/*.lef Physical description, shape and allowed orientation of cells, layer and shape of pins,blockages, antenna information, ...lib/*.lib Functional description, timing and power information, maximum load/fanout or transitiontimeallowed, ...11
Page 1 and 2: Institut für Integrierte SystemeIn
Page 3 and 4: 2 IntroductionIn this training we w
Page 5 and 6: design.cockpitrccalibredocsConfigur
Page 7 and 8: file. For power scheme 2, we would
Page 9: The OFFSET_VALUEs given in the temp
Page 13 and 14: 4 Importing the DesignStudent Task
Page 15 and 16: limits to the aspect ratio of the f
Page 17 and 18: When placing a macro-cell, you shou
Page 19 and 20: 5.4 Power PlanningThe next step is
Page 21 and 22: SPACING determines the distance bet
Page 23 and 24: In this figure, only two standard c
Page 25 and 26: 6 PlacementWe will now start with t
Page 27 and 28: The results for placement (and late
Page 29 and 30: • The columns contain numbers for
Page 31 and 32: 7.2 OptimizationIn order to (better
Page 33 and 34: • Optimization during synthesisOn
Page 35 and 36: aTake a closer look at the other tw
Page 37 and 38: A summary report is also displayed
Page 39 and 40: T clkT clkt pd ffT clkt idel t in2r
Page 41 and 42: Our example design should route wit
Page 43 and 44: • In the clock tree constraint fi
Page 45 and 46: Note: It is also possible to remove

SoC Encounter for Designers II - Integrated Systems Laboratory

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