SoC Encounter for Designers II - Integrated Systems Laboratory

avoided later on (i.e. real chip) by lowering the clock speed 32 .Further possibilities to improve timing include over-constraining the POST-CTS optimization and enablingthe TIMING DRIVEN option of NanoRoute. Earlier in the flow, TIMING DRIVEN PLACEMENTmight be worth a try. Please note that the biggest improvements are possible with ’Pre-CTS’ optimizationas the registers can be moved and resized at that stage. Per default, clock tree insertion will”fix” the registers to preserve the clock tree, i.e. they no longer can be moved or resized.Student Task 34:• If you have large ”reg2reg” setup violations, this step may take a very long time. During theinitial iterations of the design, it might be a good idea to use a more conservative (using alonger clock period) timing constraint so that not much time is spent during the optimization.Once you are satisfied with all other aspects of the design, you could revert to the originaltime constraints and let the optimizer try to achieve the timing.• Perform a postroute optimization Timing →Optimize ....• Optimization will delete and re-route all nets that are affected by the changes and run setupand hold mode timing analyses at the very end. Once again, inspect the reports.Student Task 35:• Now let us have a look at the postroute timing of our clock tree(s)enc > reportClockTree -postRouteThis will print a summary on the console and write a couple of report files chip.ctsrpt * tothe encounter directory. There should be no (or only minor) violations of our clock treeconstraints.Please note that the previous postCTS and postRoute setup (and hold) analyses alreadyconsider clock skew as they time every single path from the clock root to the leaf pinsseparately. Therefore, even a rather big skew reported here doesn’t really matter as longas the former analyses passed.So far, the clock tree has been routed as any other signal net. This is usually good enough, but if youwant, for whatever reason, to further improve clock net timings, you can do the following (in CTS):32 This does not necessarily hold true for multi-clock designs.42