SoC Encounter for Designers II - Integrated Systems Laboratory

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should consider evaluating which options are better suited rather than copying all options from thisexercise.For each standard cell, the placement algorithm will try to find the optimum location so that there is afeasible routing solution and the total length of the connections is minimized.Examine the placement by using the design browser (switch to the physical view). You will notice thatstandard cells within the same entity are mostly placed next to each other.The available space and the placement of macro-cells and I/O pads can have a great influence onthe placement of standard cells. Even though more space seems to be a good idea, too muchspace sometimes results in placements where the average distance between standard cells andconsequently the delays caused by wire capacitance/resistance become larger. Only experience andseveral iterations will allow you to find a placement for your circuit that is close to optimal.Note: Visibility of SPECIAL NET is turned off in the next screen shot.26
The results for placement (and later routing) are strongly design dependent. For example, structureswith many interconnections such as look-up tables will usually need much more space than synthesispredicted as the cells need to be spread out in order to have enough space to route all the interconnections.This is why generalizations for back-end design, such as ”During back-end design, yourcircuit area will increase by 10%” don’t work very well.Student Task 18:• Let us save the entire design with Design →Save Design As →SoCE. This will save theconfiguration file, netlist, floorplan, special route, placement and routing files as well as thecurrent mode, options and preferences. A design saved in this way can be restores usingDesign →Restore Design ... →SoCE.The space required is surprisingly small as most files are compressed and the library filesdo not get saved along with the design.• Remember to save under the save directory.Alternatively you could also just save the placement. Select Design →Save →Place \....During synthesis, SYNOPSYS DESIGN COMPILER assigns constant logic values to two special standardcells named TIE0x and TIE1x, where x is a drive strength modifier. This creates a smallinconvenience, as often one of these cells is assigned to drive many outputs at the same time, creatingrelatively long interconnections.There is sufficient place on the chip to place several of these cells. We will use a script that firstremoves all these cells. Then we will set the rules for placing these cells. The example script scripts\/tiehilo.tcl sets the maximum number of connections driven by a single cell to 20, and the maximumdistance between the pin and the tie cell to 250 µm. And finally we insert the tie cells according tothe rules we have defined.Student Task 19:• At the command line type:enc >source scripts/tiehilo.tcl7 TimingThe synthesis tools we currently use for HDL synthesis (SYNOPSYS DESIGN COMPILER) are notaware of any instance placement information. Therefore the interconnects can only be estimatedbased on a statistical model, i.e. the fanout of a net determines its length, capacitance, resistance andarea. Now that the placement and even trial-routing is available the timing might differ considerablyfrom the numbers obtained from SYNOPSYS DESIGN COMPILER.7.1 AnalysisCADENCE SOC ENCOUNTER has a practical timing analysis function, where you only have to specifythe state of the design (see below) and the ANALYSIS TYPE (Setup or Hold) you want to run.27
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Page 13 and 14: 4 Importing the DesignStudent Task
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Page 19 and 20: 5.4 Power PlanningThe next step is
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SoC Encounter for Designers II - Integrated Systems Laboratory

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