SoC Encounter for Designers II - Integrated Systems Laboratory

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12 FinishingWe are almost done with backend design, there are only a few steps required to finish the layout andverify that everything is correct.12.1 Insert Filler CellsStudent Task 36:• Now that we don’t need the additional space within the standard cell rows anymore, wehave to fill these gaps with filler cells. This is required for fabrication. In addition, some ofthem contain capacitors between VCC and GND that filter spikes on the power lines.enc >source scripts/fillcore.tclNote that your row utilization will be 100% after this step. This means that you will have no roomfor further optimizations. Make sure to insert filler cells after all optimizations have been completed.44
Note: It is also possible to remove the filler cells with Place →Filler →Delete... or by usingthe script removefillcore.tcl.12.2 Checking Connectivity and Geometry ViolationsNow that we are completely finished with the layout, we should make sure that we have no connectionerrors, i.e. all logic connections from the netlist are also present in the physical layout.Student Task 37:• Select Verify →Verify Connectivity ... from the menu. A window will appear.Run the analysis and check the console for the report summary. There should be noviolations.• In a similar way let us verify all geometrical shapes. Select Verify →Verify Geometry \... from the menu. Run the analysis and check the report on the console. You should getno violations.There is a script that will perform the last verification steps for you automatically. You can set avariable DESIGNNAME to assign the base name for all the files generated by this script.enc > set DESIGNNAME MyBeautifulChipenc > source scripts/checkdesign.tcl45
Page 1 and 2: Institut für Integrierte SystemeIn
Page 3 and 4: 2 IntroductionIn this training we w
Page 5 and 6: design.cockpitrccalibredocsConfigur
Page 7 and 8: file. For power scheme 2, we would
Page 9 and 10: The OFFSET_VALUEs given in the temp
Page 11 and 12: 3.2.3 Timing ConstraintsJust as for
Page 13 and 14: 4 Importing the DesignStudent Task
Page 15 and 16: limits to the aspect ratio of the f
Page 17 and 18: When placing a macro-cell, you shou
Page 19 and 20: 5.4 Power PlanningThe next step is
Page 21 and 22: SPACING determines the distance bet
Page 23 and 24: In this figure, only two standard c
Page 25 and 26: 6 PlacementWe will now start with t
Page 27 and 28: The results for placement (and late
Page 29 and 30: • The columns contain numbers for
Page 31 and 32: 7.2 OptimizationIn order to (better
Page 33 and 34: • Optimization during synthesisOn
Page 35 and 36: aTake a closer look at the other tw
Page 37 and 38: A summary report is also displayed
Page 39 and 40: T clkT clkt pd ffT clkt idel t in2r
Page 41 and 42: Our example design should route wit
Page 43: • In the clock tree constraint fi

SoC Encounter for Designers II - Integrated Systems Laboratory

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