SoC Encounter for Designers II - Integrated Systems Laboratory

Let’s now examine the detailed reports that were generated by timing analysis and can be found inthe timingReports folder. Each analysis produces multiple files. Among these there are three filesdedicated to design rule violations (max capacitance: * .cap , max fanout: * .fanout, max transitiontime: * .tran violations), and separate *.tarpt timing analysis report files for different path groups(in2out, in2reg, reg2reg, reg2out)Student Task 21:• Where do the violating paths in the in2out path category start?• Where do the violating paths in the in2reg path category start?• Do the paths in reg2out and reg2reg look like normal path that should be optimized tomeet timing or is there something wrong?• Why are the reg2reg paths too slow? Look for large numbers in the Delay column andcheck the drive strength of the corresponding cell.There are several different problems in the .sdc file that we have used. First of all, two of our inputsshould not be considered for timing analysis 28 . We also have several nets (clock, reset and scanenable) that we will take care of separately (using the clock tree synthesizer, which we will see later).These nets will show up in the DRV reports. We do not want to solve timing related problems forthese nets (since they will anyway be solved later), the time and effort required to optimize these netscould prevent other parts of the design to be optimized.We can use the DEFAULT PIN LIMIT feature of CADENCE SOC ENCOUNTER to stop CADENCE SOCENCOUNTER from extracting timing information (and reporting timing violations) for the nets that wewill be optimizing later on. By default the pin limit of CADENCE SOC ENCOUNTER is set to 1000. Inour case this number is too high (we have slightly more than 400 flip flops in our design).Student Task 22:• Let us see the nets which have a large fanout. Report all nets with e.g. more than 400 pins.Use the console command:enc > report_net -min_fanout 400• Now set a suitable limit with the commandenc >setUseDefaultDelayLimit so that the high fanout nets will not be considered for timing. Also make the necessarychanges to the timing constraints file src/chip.sdc to disable the offending inputports.Reload the timing constraints by selecting the menu Timing →Load Timing \Constraint ....• Then rerun timing analysis.If you have done everything correct, the only setup violations should be in the path group registerto-registerand register-to-out. There should no longer be pins that belong to scan enable or resetnetwork in the transition time violation report.28 Cadence SoC Encounter provides a special timing calculation mode that is called Multi-Mode Multi-CornerAnalysis (MMMC). In this mode it is possible to define several scenarios (i.e. separate test and functional modes).The setup for MMMC is slightly involved and will not be covered as part of this exercise.30