SoC Encounter for Designers II - Integrated Systems Laboratory

Clock Our main concern is to reduce the skew, since it will effect our timing. The maximum skewdepends on the clock period. As an example, for a 20 MHz clock a clock skew of 0.5 ns isacceptable. But for a 200 MHz clock, the same skew equals to 10% of the clock period andwould be to high.If you over-constrain your skew, you will need a deep (and large) clock tree and your insertiontime will rise, which will affect your input and output timing. Therefore you will want to balancethe skew against insertion delay and the number of buffers. Constraining maximum insertiondelay too low will usually degrade results.Usually, a tree that gives you an acceptable skew will also give you a decent transition time, soyou don’t have to worry about that.Reset We are interested in propagating the reset within one clock cycle to all flip-flops in our design.For designs with on-chip reset synchronization this is strictly required. The insertion delayshould therefore be less than the clock period, transition times within the bounds imposed bythe technology and skew doesn’t matter at all.Scan Enable Very similar to the reset signal. Usually a slower clock is used for scan testing, thereforewe can allow even a larger insertion delay. For transition time and skew the same holds true asfor the reset.Buf TranSink TranSink TranAutoCTSRoot PinBuf TranSink TranBuf TranSink TranMin DelayMax DelayMax SkewIn CADENCE SOC ENCOUNTER , clock tree synthesis (CTS) is used to generate optimized buffertrees to drive high fan-out nets. It can be configured to satisfy a variety of constraints.Student Task 26:• A sample clock tree synthesis configuration file can be found under src/sample/chip.ctstch\−sample. The sample file contains three different configurations for a clock, a reset and ascan enable signal.• Copy this file to the src directory and adapt the ’AutoCTSRootPin’ statements to matchyour design.• For educational purposes, change the clock tree specifications as follows: max. skew0.2 ns, max. insertion delay 4 ns, max. transition time at buffers 0.6 ns and at clock pins0.4 ns a 34