SoC Encounter for Designers II - Integrated Systems Laboratory

Let’s start with the first category.3.2.1 Verilog NetlistThe Verilog netlist we obtain from synthesis contains standard cells, functional I/O pads and theirinterconnection information. While the functionality including scan circuitry is already complete, somespecial cells are still missing:• Supply pads to provide power and ground to the core (pads ’VCCKD’ and ’GNDKD’) and to thepadframe (pads ’VCC3IOD’ and ’GNDIOD’).• Corner pads that need to be placed in the corners of the padframe to complete the power linesrunning inside the padframe (pad CORNERD).Due to the arrangement we have with our ASIC manufacturer, student designs are strictly limited insize. As a consequence at most 56 pads (not including the 4 corner pads) can be placed in thepadframe. Furthermore, to ease chip testing on the ASIC tester two predefined power schemes havebeen established:1. 40 signal pads, 16 supply padsTake a look at the following web page for an illustration of the power schemes and to obtain furtherinformation on constraints for the semester design projects.http://www.eda.ee.ethz.ch/index.php/UmcL180#Mini.40sicWith all this information we are now ready to add the missing corner and supply pads to our Verilognetlist.A typical Verilog netlist that you will obtain from SYNOPSYS DESIGN COMPILER will contain manylevels of hierarchy. Each level of hierarchy is enclosed between themodule name ( pin names separated by comma )...endmodulestatements, where ’name’ refers to the name of the module (module is the Verilog equivalent of anentity in VHDL). In our case we need to add the pads to the top-level module which contains the restof the I/O pads. The top-level design is almost always the last module definition in a Verilog file 3 .Student Task 2:• Copy the Verilog netlist to encounter/src/ in order to have a clean copy of the initial netlisteven if synthesis is rerun.sh > cd encounter/src/sh > cp -p ../../synopsys/netlists/filter_chip.v \filter_chip.v.initialThe file specialpads.v contains four corner pads and 8 supply pads corresponding to thepower scheme 1. As our design uses power scheme 1, no changes are required to this3The content of the module needs to be defined before it can be instantiated by a different module. Consequently thetop-level module is the last to be defined, however not all Verilog files need to be hierarchical, a design can also bespread between multiple files6