SoC Encounter for Designers II - Integrated Systems Laboratory

Larger values will reduce the area available to place the core cells thereby increasing coreutilization.As noted earlier, some iterations are usually required to find optimal values for a particulardesign.• In this exercise we will assume that we will use one VCC and one GND line of maximumwidth 20 µm. We need some extra space between the lines and, for the moment, we canstart with a distance of 50 µm for all sides and click on OK.The floorplan should now look like shown in the screen-shot below. Note that the pads are all placedat their proper locations as the I/O file used during design import specifies absolute locations and wemade sure that the die size stays fixed to the proper size during the initialize floorplan step.Student Task 8:• Next we need to place the RAM macro-cell. Change the cursor mode to MOVE/RESIZE/RE-SHAPE by selecting the appropriate icon (next to the ruler icon) or use the keyboard shortcut’SHIFT-R’. Now you can select the RAM macro-cell and drag it to any location you like. Theblue lines displayed are so called flightlines that show where the signal connections to theblock are.You can change the orientation of the RAM by either using Floorplan →Edit Floorplan→\Flip/Rotate Instances ... (or press ’r’), or with the attribute editor (press ’q’). Note that theRAM macro will completely block Metal-1, Metal-2, Metal-3 and Metal-4. Only Metal-5,Metal-6 will be available for routing over the RAM macro-cell 20 .20 By default, the internal structures within a cell or block are not displayed. You need to make “Cell Blkg” visible tosee the so called blockages within a cell.18