SoC Encounter for Designers II - Integrated Systems Laboratory

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)(iopad(topleft[pads that are on the top left])(left[pads that are on the left side]))[definitions for other sides]For us the relevant part is the iopad section. This part contains eight subsections that define thenames of the pad instances, and their locations in the four sides and four corners. We do not haveto touch the corner specifications 7 as they will be the same for all designs. We have to distribute thepads among the four sides of the chip top, right, bottom, left. If you look at the sample file youwill see that for each pad there is a single line entry in the following form(inst name="NAME_OF_PAD"offset=OFFSET_VALUE ) # pin no: PIN_NUMBERThe last part following # is a comment, it is there just for your information. Regardless of the powerscheme you are using, we will use the same 56 pin package as illustrated in the webpage above.The PIN_NUMBER is just a reminder to show which particular location is being defined. The locationis specified using the OFFSET_VALUE. CADENCE SOC ENCOUNTER uses a coordinate system thatbases the coordinate (0,0) on the bottomleft corner as shown in the figure below:toplefttoptopright123leftrightSideOffset0,0bottomleftbottombottomrightOn the left and right side the pads will be ordered from bottom-to-top, and on the top andbottom side the pads will be ordered from left-to-right. This ordering can be quite confusing, asit is neither clockwise, nor counterclockwise. Therefore the aforementioned comments showing theactual pin numbers will be very useful.7topleft, topright, bottomleft, bottomright8
The OFFSET_VALUEs given in the template represent fixed locations for the given pad. It is veryimportant that you do not change these values, as the chip-finishing part will rely on the pads beinglocated exactly at these locations.You can assign your pads by writing the name of each pad into the corresponding NAME_OF_PAD.The name of the pad will be the name of the instance in the Verilog file. For example assume that youare using standard power scheme and your clock signal is assigned to a pad named pad_clock. Inyour Verilog file you would have the following entry for this pad:XMD ClkxCI_PAD ( .I(ClkxCI) [other pin definitions] )If you now want to place this pad on pin number 54 of your package, you will find the subsection topin the I/O file and edit the line for pin 54:...(iopad...(top...(inst name="ClkxCI_PAD" offset= 864.28 ) # pin no: 48...)...)Be careful, do not modify the offset value while you are editing the I/O file. Since we use a fixedbonding scheme for the power and ground pins, all we need to do is extract the instance names forall our signal pads and place them by inserting within the appropriate inst name="" statement correspondingthe OFFSET_VALUE which corresponds to the desired location. It is also recommendedto put the clock pin (if possible) to pin number 48. All new test boards will make sure that the pin 48has the best signal quality.Preparing the I/O file from scratch can be a lengthy and tedious task. To avoid unnecessary workduring this exercise we will start with an almost complete I/O file, but before doing so we will describethe full procedure recommended when starting from scratch:1. Start CADENCE SOC ENCOUNTER and proceed to design import 8 by selecting Design→\Import Design. In this form make sure that the IO ASSIGNMENT FILE is empty.2. If everything works well, the design will be loaded. Now we can write out a template file that willcontain all the names of the pads. Use Design→Save →I/O File ... to save an I/O filesrc/chip−sequence.io. You can select the SEQUENCE checkbox, however it is not imperative.What we need is only the names of the pads.3. Copy the template I/O file src/sample/chip.io−template to src/chip.io. As noted earlier, this fileincludes all offset= statements, and all statements for corner and supply pads.4. Using a text editor open the files src/chip.io and src/chip−sequence.io. You need to move thePAD_NAMEs from the file src/chip−sequence.io to the correct positions in the file src/chip.io.5. All entries for data pins in the template file are by default commented out using ‘#‘ character.Do not forget to remove the comment character for the pads you are using.8Importing the design will be covered in detail in Chapter 4.9
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SoC Encounter for Designers II - Integrated Systems Laboratory

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