SoC Encounter for Designers II - Integrated Systems Laboratory

We are now in the floorplan view of CADENCE SOC ENCOUNTER which displays an empty floorplanwith only the pads placed. All top level module(s) of the netlist are shown as a pink/purple square tothe left and all macro-cells to the right. Note that all standard cells are inside the module(s).5 FloorplanningNow we will have to decide how cells and macro-cells will be placed on our chip. This process iscalled floorplanning. For a standard design, our main concern would be to find a floorplan that willresult in the smallest possible area, while fulfilling all performance and reliability requirements. Thisis purely driven by economical reasons, since chip costs are mainly determined by the area. In somecases there are additional geometrical constraints. The manufacturing company may impose certain14