SoC Encounter for Designers II - Integrated Systems Laboratory

12.3 Evaluate the Physical DesignTake the time to examine the routing. This is the main feedback you need for a second back-enditeration. Try to view all metal lines separately to see how congested your routing is. If you see a lotof Metal-6 (orange) you are probably close to the density limit. In our design you should not noticeany congestion and Metal-6 will barely be used. If your design routed without problems and therouting was rather sparse then the next time you could assign a smaller core area and increase therow utilization. On the other hand if the design barely routed you have found the limits, in a seconditeration you might consider assigning a little more core area timing degrades with congestion.Check the connections of your macro-cells and pads, this may give you an idea how to place themacro-cells the next time around. You need to get used to evaluating the result of different back-enddesign runs.12.4 Generate Output FilesCongratulations, you have completed the back-end design. That was not so hard now, was it?Student Task 38:• Save your design using Design →Save Design As ... →SoCE to the save directoryand make sure that you use a name that shows this is a finished design (i.e. chip final.enc).• Finally we need to export all data needed for post layout simulation and physical verification(DRC/LVS). There is a script that will write out all relevant files to the out/ directory a .enc >source scripts/exportall.tclaTo get complete supply net connectivity in the Verilog netlist for LVS, the missing connections for the powerand ground pins (GNDIO/VCC3IO) of the pads are added and removed on-the-fly. We could also define andhandle these two nets in the same way as VCC/GND, but there are more drawbacks than benefits.Similar to the checkdesign.tcl file, the variable DESIGNNAME will be used to assign the base name ofthe files. If you do not specify a name, final will be used. After you complete this step you will havethe following files:*.v This is the final netlist. Make sure to use this netlist for post layout simulations.*.gds.gz The layout in GDSII (Graphic Design System II) format. This is the standard format forexchanging layout data.*.sdf.gz The SDF (Standard Delay Format) file to be used for post layout simulation.46