SoC Encounter for Designers II - Integrated Systems Laboratory

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Pin DescriptionsName Bits Dir DescriptionClkxCI 1 In Clock inputResetxRBI 1 In Reset input, active low signal, 0: ResetScanEnxTI 1 In Scan Enable for testing, 1: ScanRamTestxTI 1 In Ram bypass control, 1: Test (RAM bypassed)DataInxDI 16 In 16-bit data inputDataInReqxSI 1 In Request signal for data inputDataInAckxSO 1 Out Acknowledge signal for data inputDataOutxDO 16 Out 16-bit data outputDataOutReqxSO 1 Out Request signal for data outputDataOutAckxSI 1 In Acknowledge signal for data output3 Getting StartedYou will need a terminal program to type in commands throughout this exercise. In the computersin the ETZ D61.2 you can get a terminal by accessing the menu on the top left corner and selectingApplications→Accessories→Terminal.Student Task 1:• Change to your home directory and install the training files with the script provided:sh >sh >cd ˜/home/vlsi2/t1/install_t1• Change to the design directorysh >cd training_1The copied files and folders are arranged in a certain structure which is described in the next section.3.1 Directory StructureThe following figure shows the directory structure for a design directory that was created by thecockpit tool developed by the Design Zentrum (DZ) of ETH Zurich.4
design.cockpitrccalibredocsConfiguration for the cockpitFinal layout, DRC and LVSLinks to documentsencounteroutsavescriptssrctechFinal output files: netlist, layout, timing (Verilog,GDSII, SDF)Save files for Encounter (Encounter native format)Example scripts, run scripts (TCL)Input source files: netlist, constraints, io placementsample Sample input filesLinks to technology files, etc.lef Links to absracts and technologylib Links to timing librariesmodelsimsimvectorssourcecodesynopsystetramaxSimulation toolStimuli and expected responsesVHDL sourcecodeSynthesis environmentTest vector generation, test coverageIn this structure, there are five subdirectories for CADENCE SOC ENCOUNTER . It is strongly recommendedto use them in the following way:out Place all final data to be exported from CADENCE SOC ENCOUNTER in this directory. Thisincludes the final netlist (the initial netlist gets modified by clock tree insertion, optimization etc.),layout and delay files that will be used for postlayout simulation and/or physical verification andchip finishing. A sample script that generates all these files is provided (scripts/exportall.tcl).save Put all CADENCE SOC ENCOUNTERformat, in this directory.save files, i.e. files in native CADENCE SOC ENCOUNTERscripts Contains TCL scripts. By default several example scripts for common tasks are provided. Itis highly recommended to develop a run script that contains all the commands used for yourdesign.src All user input files should be placed here. These include the initial Verilog netlist, the I/O placementfile, timing constraints file and clock tree definition file (all will be explained later in section3.2).tech Holds links to technology specific files. Cockpit manages this directory automatically.3.2 Input FilesThe input files required for back-end design with CADENCE SOC ENCOUNTERtwo categories:can be divided into• Design files that describe (or are closely related with) the circuit, first of all the Verilog netlist ofour synthesized design.• Technology files that describe the technology itself as well as libraries of standard buildingblocks implemented in this technology.5
Page 1 and 2: Institut für Integrierte SystemeIn
Page 3: 2 IntroductionIn this training we w
Page 7 and 8: file. For power scheme 2, we would
Page 9 and 10: The OFFSET_VALUEs given in the temp
Page 11 and 12: 3.2.3 Timing ConstraintsJust as for
Page 13 and 14: 4 Importing the DesignStudent Task
Page 15 and 16: limits to the aspect ratio of the f
Page 17 and 18: When placing a macro-cell, you shou
Page 19 and 20: 5.4 Power PlanningThe next step is
Page 21 and 22: SPACING determines the distance bet
Page 23 and 24: In this figure, only two standard c
Page 25 and 26: 6 PlacementWe will now start with t
Page 27 and 28: The results for placement (and late
Page 29 and 30: • The columns contain numbers for
Page 31 and 32: 7.2 OptimizationIn order to (better
Page 33 and 34: • Optimization during synthesisOn
Page 35 and 36: aTake a closer look at the other tw
Page 37 and 38: A summary report is also displayed
Page 39 and 40: T clkT clkt pd ffT clkt idel t in2r
Page 41 and 42: Our example design should route wit
Page 43 and 44: • In the clock tree constraint fi
Page 45 and 46: Note: It is also possible to remove

SoC Encounter for Designers II - Integrated Systems Laboratory

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