SoC Encounter for Designers II - Integrated Systems Laboratory

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Pre-Place design is not placedPre-CTS design is placed but clock tree is not yet insertedPost-CTS design is placed and the clock tree is insertedPost-Route design is placed and routedSign-Off will use extra tools for even more precise analysis. We will not use this as these tools arenot installed/setup.Depending on this state, trial route (a very simple, but fast routing) and/or parasitic extraction mightbe run automatically prior to the timing analysis. This will improve the accuracy and help to avoidunnecessary iterations.Student Task 20:• Open Timing →Analyze Timing and make sure PRE-CTS and SETUP is selected.• Start the timing analysis by clicking OK.Note: You could also do this from the command line withenc >timeDesign -preCTSAs the design is not routed, CADENCE SOC ENCOUNTER will perform trial route and parasitic extractionbefore doing the timing analysis. A short summary will be displayed on the console (the actualnumbers may differ slightly):+--------------------+---------+---------+---------+---------+---------+---------+| Setup mode | all | reg2reg | in2reg | reg2out | in2out | clkgate |+--------------------+---------+---------+---------+---------+---------+---------+| WNS (ns):| -9.069 | -6.554 | -9.069 | -0.686 | -7.328 | N/A || TNS (ns):| -2684.3 | -1776.9 | -2392.1 | -1.172 | -43.761 | N/A || Violating Paths:| 861 | 732 | 454 | 7 | 6 | N/A || All Paths:| 1807 | 1342 | 817 | 18 | 6 | N/A |+--------------------+---------+---------+---------+---------+---------+---------++----------------+-------------------------------+------------------+| | Real | Total || DRVs +------------------+------------+------------------|| | Nr nets(terms) | Worst Vio | Nr nets(terms) |+----------------+------------------+------------+------------------+| max_cap | 187 (187) | -3.774 | 188 (188) || max_tran | 368 (13826) | -8.333 | 387 (13867) || max_fanout | 0 (0) | 0 | 0 (0) |+----------------+------------------+------------+------------------+Density: 59.566%Routing Overflow: 0.00% H and 0.25% V------------------------------------------------------------The summary gives a very good overview of the current design timing. Some explanations:• The analysis was run in setup mode, i.e. setup time checks were performed but no hold timechecks.28
• The columns contain numbers for all path in the design (ALL) or for specific path groups, e.g.reg2reg for all register to register paths.• Worst negative slack (WNS) reports the slack for the most critical path.mean that the constraints are violated by this value.Negative numbers• Total negative slack (TNS) is the sum of WNS for all violating paths. Together with the numberof violating paths this figure helps to see how severe the violations are.• Real/Total DRV show (electrical) design rule violations, some libraries have a maximum transitiontime for all nets. The report above shows that 370 nets have a transition violation (thesignal takes too long to change from logic-1 to logic-0 or vice versa). In addition 135 nets havea maximum capacitance violation (the total amount of capacitance driven by a net exceeds thelimit set by the design library). These violations are mostly related to excessive parasitic capacitancedue to interconnections, and generally cause timing violations as well. However, even ifa DRV does not cause a timing violation it needs to be fixed.• DENSITY and ROUTING OVERFLOW show the placement utilization and routing resources, i.e.are a measure for the feasibility of the current floorplan/placement.Remark: Refer to exercise 4 of VLSI I 25 if you have problems with timing concepts.The summary looks really terrible. Obviously we have many timing violations that we need to have acloser look at, before we try to optimize the timing with CADENCE SOC ENCOUNTER .Here are some important points to consider when doing so:• The timing depends entirely on the constraints you have specified in the file src/chip.sdc. Themost common mistake is to have errors in this file. Before you go any further make sure thatyour timing constraints are correct.• Make sure to not accidentally use constraints that were written for the core level (chip withoutpads) at the chip level (with pads) and vice versa. The pads affect the I/O timing quite a bit andthe drive capabilities of a standard cell and an output pad are entirely different, i.e. set_loadneeds to be very different.• Inputs and outputs used for test and debugging may cause timing violations. Most of thesesignals are not dynamic (they are not toggled during normal operation) and the timing pathsoriginating from these inputs or ending at these outputs should be ignored, i.e. left unconstrainedor explicitly disabled.• To speed up delay calculation CADENCE SOC ENCOUNTER does not compute the timing ofnets with a fanout above a certain limit but rather swaps in predefined values for delay, capacitanceand transition time. All these numbers are specified on the DESIGN IMPORT form on theADVANCED tab in the ”Delay Calculation” category. As a result you will not see the real timing 26of these net in timing analysis and furthermore optimization will not see (and therefore not fix)violations 27 on these nets. However, this is usually the desired behavior as we give these netsa special treatment anyway (with CTS).25 You can access the exercise descriptions, files, and solutions under /home/vlsi1/u4.26 To see the real timing you can change the limit on-the-fly from 1000 to a very high value in the console withsetUseDefaultDelayLimit 100000. More on this topic later.27 DRV violations will be fixed but no setup/hold violations. Clock nets are even more special, also no DRV fixing willbe done there.29
Page 1 and 2: Institut für Integrierte SystemeIn
Page 3 and 4: 2 IntroductionIn this training we w
Page 5 and 6: design.cockpitrccalibredocsConfigur
Page 7 and 8: file. For power scheme 2, we would
Page 9 and 10: The OFFSET_VALUEs given in the temp
Page 11 and 12: 3.2.3 Timing ConstraintsJust as for
Page 13 and 14: 4 Importing the DesignStudent Task
Page 15 and 16: limits to the aspect ratio of the f
Page 17 and 18: When placing a macro-cell, you shou
Page 19 and 20: 5.4 Power PlanningThe next step is
Page 21 and 22: SPACING determines the distance bet
Page 23 and 24: In this figure, only two standard c
Page 25 and 26: 6 PlacementWe will now start with t
Page 27: The results for placement (and late
Page 31 and 32: 7.2 OptimizationIn order to (better
Page 33 and 34: • Optimization during synthesisOn
Page 35 and 36: aTake a closer look at the other tw
Page 37 and 38: A summary report is also displayed
Page 39 and 40: T clkT clkt pd ffT clkt idel t in2r
Page 41 and 42: Our example design should route wit
Page 43 and 44: • In the clock tree constraint fi
Page 45 and 46: Note: It is also possible to remove

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